Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932482AbcCJV0M (ORCPT ); Thu, 10 Mar 2016 16:26:12 -0500 Received: from mga02.intel.com ([134.134.136.20]:55967 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932216AbcCJV0K (ORCPT ); Thu, 10 Mar 2016 16:26:10 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,317,1455004800"; d="scan'208";a="907362007" From: "Fenghua Yu" To: "H. Peter Anvin" , "Ingo Molnar" , "Thomas Gleixner" , "Ravi V Shankar" Cc: "linux-kernel" , "x86" , "Fenghua Yu" Subject: [PATCH v2] x86/cpufeatures.h: Enumerate A Few New AVX-512 Features Date: Thu, 10 Mar 2016 16:23:48 -0800 Message-Id: <1457655828-35106-1-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 1.8.0.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1778 Lines: 40 From: Fenghua Yu A few new AVX-512 instruction groups/features are added in cpufeatures.h for enuermation: AVX512DQ, AVX512BW, and AVX512VL. The specification for latest AVX-512 including the features can be found at https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Signed-off-by: Fenghua Yu --- v2: Change cpufeature.h to cpufeatures.h to use right file name in latest kernel. arch/x86/include/asm/cpufeatures.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 1a2811f..9ba2ca9 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -220,6 +220,7 @@ #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ +#define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ Instructions */ #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ #define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */ #define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ @@ -230,6 +231,8 @@ #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ #define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ +#define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW Instructions */ +#define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 Vector Lengths */ /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ -- 2.5.0