Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932672AbcCMJIz (ORCPT ); Sun, 13 Mar 2016 05:08:55 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:34344 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932557AbcCMJIe (ORCPT ); Sun, 13 Mar 2016 05:08:34 -0400 From: Caesar Wang To: Heiko Stuebner , "David S. Miller" , Rob Herring Cc: linux-rockchip@lists.infradead.org, keescook@google.com, leozwang@google.com, sergei.shtylyov@cogentembedded.com, netdev@vger.kernel.org, Xing Zheng , Caesar Wang , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/9] clk: rockchip: add clock-id for rk3036 emac pll source clock Date: Sun, 13 Mar 2016 17:07:40 +0800 Message-Id: <1457860062-5514-8-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1457860062-5514-1-git-send-email-wxt@rock-chips.com> References: <1457860062-5514-1-git-send-email-wxt@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 847 Lines: 30 From: Xing Zheng Suitable PLLs for the emac on the rk3036 are difficult to find and one of them is the (continuously changing) APLL. So in most cases it will be necessary to select a PLL manually. So add a clock-id for it. Signed-off-by: Xing Zheng Signed-off-by: Caesar Wang --- Changes in v2: None include/dt-bindings/clock/rk3036-cru.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h index 3396591..de44109 100644 --- a/include/dt-bindings/clock/rk3036-cru.h +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -54,6 +54,7 @@ #define SCLK_PVTM_VIDEO 125 #define SCLK_MAC 151 #define SCLK_MACREF 152 +#define SCLK_MACPLL 153 #define SCLK_SFC 160 /* aclk gates */ -- 1.9.1