Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753967AbcCMJJ4 (ORCPT ); Sun, 13 Mar 2016 05:09:56 -0400 Received: from mail-pf0-f194.google.com ([209.85.192.194]:36247 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932413AbcCMJIi (ORCPT ); Sun, 13 Mar 2016 05:08:38 -0400 From: Caesar Wang To: Heiko Stuebner , "David S. Miller" , Rob Herring Cc: linux-rockchip@lists.infradead.org, keescook@google.com, leozwang@google.com, sergei.shtylyov@cogentembedded.com, netdev@vger.kernel.org, Caesar Wang , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 8/9] clk: rockchip: associate SCLK_MAC_PLL and disable reparenting on rk3036 Date: Sun, 13 Mar 2016 17:07:41 +0800 Message-Id: <1457860062-5514-9-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1457860062-5514-1-git-send-email-wxt@rock-chips.com> References: <1457860062-5514-1-git-send-email-wxt@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1250 Lines: 31 From: Heiko Stuebner The emac needs constant and very specific rate but the possible PLL-sources are very limited, so we expect the PLL source to be set manually on per board and don't want it to get changed in an automatic way later. So add the necessary clock-id and disable reparenting on set_rate calls. Signed-off-by: Heiko Stuebner Signed-off-by: Caesar Wang --- Changes in v2: None drivers/clk/rockchip/clk-rk3036.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c index cc66e5f..7cdb2d6 100644 --- a/drivers/clk/rockchip/clk-rk3036.c +++ b/drivers/clk/rockchip/clk-rk3036.c @@ -348,7 +348,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS, RK2928_CLKGATE_CON(10), 5, GFLAGS), - COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0, + COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src", mux_pll_src_3plls_p, CLK_SET_RATE_NO_REPARENT, RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS), MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(21), 3, 1, MFLAGS), -- 1.9.1