Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933315AbcCNBNa (ORCPT ); Sun, 13 Mar 2016 21:13:30 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:61987 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932584AbcCNBNS (ORCPT ); Sun, 13 Mar 2016 21:13:18 -0400 Subject: Re: [PATCH 2/3] net: hns: add Hisilicon RoCE support To: Lijun Ou , , , , , , , , , , , , , , , , , , References: <1457692631-9290-1-git-send-email-oulijun@huawei.com> <1457692631-9290-3-git-send-email-oulijun@huawei.com> <20160312104301.GB15703@leon.nu> From: "Yankejian (Hackim Yim)" Message-ID: <56E60FFC.3000007@huawei.com> Date: Mon, 14 Mar 2016 09:12:28 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <20160312104301.GB15703@leon.nu> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.57.126.191] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090202.56E61007.0013,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 9fa393499f15d0d6f7f15839f779a2cf Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3107 Lines: 103 On 2016/3/12 18:43, Leon Romanovsky wrote: > On Fri, Mar 11, 2016 at 06:37:10PM +0800, Lijun Ou wrote: >> It added hns_dsaf_roce_reset routine for roce driver. >> RoCE is a feature of hns. >> In hip06 SOC, in roce reset process, it's needed to configure >> dsaf channel reset,port and sl map info. >> >> Signed-off-by: Lijun Ou >> Signed-off-by: Wei Hu(Xavier) >> Signed-off-by: Lisheng >> --- >> drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c | 84 ++++++++++++++++++++++ >> drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h | 14 ++++ >> drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c | 62 +++++++++++++--- >> drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h | 13 ++++ >> 4 files changed, 163 insertions(+), 10 deletions(-) >> >> diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c >> index 38fc5be..a0f0d4f 100644 >> --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c >> +++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c >> @@ -12,6 +12,7 @@ >> #include >> #include >> #include >> +#include >> #include >> #include >> #include >> @@ -2593,6 +2594,89 @@ static struct platform_driver g_dsaf_driver = { >> >> module_platform_driver(g_dsaf_driver); >> >> +/** >> + * hns_dsaf_roce_reset - reset dsaf and roce >> + * @dsaf_fwnode: Pointer to framework node for the dasf >> + * @val: 0 - request reset , 1 - drop reset >> + * retuen 0 - success , negative --fail >> + */ >> +int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, u32 val) >> +{ >> + struct dsaf_device *dsaf_dev; >> + struct platform_device *pdev; >> + unsigned int mp; >> + unsigned int sl; >> + unsigned int credit; >> + int i; >> + const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE] = { >> + {0, 0, 0}, >> + {1, 0, 0}, >> + {2, 1, 0}, >> + {3, 1, 0}, >> + {4, 2, 1}, >> + {4, 2, 1}, >> + {5, 3, 1}, >> + {5, 3, 1}, >> + }; >> + const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE] = { >> + {0, 0, 0}, >> + {0, 1, 1}, >> + {0, 0, 2}, >> + {0, 1, 3}, >> + {0, 0, 0}, >> + {1, 1, 1}, >> + {0, 0, 2}, >> + {1, 1, 3}, >> + }; > Do you have a plan to send a version with enums/defines for this > numbers? Especially for _CHAN_MODE. > > . Hi leon, it seems the enums is added in hns_dsaf_main.h, as belows: diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h index 5fea226..c917b9a 100644 --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h +++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h @@ -40,6 +40,16 @@ struct hns_mac_cb; #define DSAF_DUMP_REGS_NUM 504 #define DSAF_STATIC_NUM 28 +#define DSAF_ROCE_CREDIT_CHN 8 +#define DSAF_ROCE_CHAN_MODE 3 + +enum dsaf_roce_port_port_mode { + DSAF_ROCE_6PORT_MODE, + DSAF_ROCE_4PORT_MODE, + DSAF_ROCE_2PORT_MODE, + DSAF_ROCE_CHAN_MODE_NUM +}; + MBR, Kejian