Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964851AbcCNIFU (ORCPT ); Mon, 14 Mar 2016 04:05:20 -0400 Received: from mail-pa0-f66.google.com ([209.85.220.66]:36329 "EHLO mail-pa0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933905AbcCNIDr (ORCPT ); Mon, 14 Mar 2016 04:03:47 -0400 From: Caesar Wang To: Heiko Stuebner , "David S. Miller" , Rob Herring Cc: linux-rockchip@lists.infradead.org, keescook@google.com, leozwang@google.com, sergei.shtylyov@cogentembedded.com, netdev@vger.kernel.org, Xing Zheng , Caesar Wang , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 7/9] clk: rockchip: add clock-id for rk3036 emac pll source clock Date: Mon, 14 Mar 2016 16:01:58 +0800 Message-Id: <1457942520-12859-8-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1457942520-12859-1-git-send-email-wxt@rock-chips.com> References: <1457942520-12859-1-git-send-email-wxt@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1121 Lines: 40 From: Xing Zheng Suitable PLLs for the emac on the rk3036 are difficult to find and one of them is the (continuously changing) APLL. So in most cases it will be necessary to select a PLL manually. So add a clock-id for it. Signed-off-by: Xing Zheng Signed-off-by: Caesar Wang Cc: Xing Zheng Cc: Michael Turquette Cc: Heiko Stuebner Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-rockchip@lists.infradead.org --- Changes in v3: - Add the Cc people. Changes in v2: None include/dt-bindings/clock/rk3036-cru.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h index 3396591..de44109 100644 --- a/include/dt-bindings/clock/rk3036-cru.h +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -54,6 +54,7 @@ #define SCLK_PVTM_VIDEO 125 #define SCLK_MAC 151 #define SCLK_MACREF 152 +#define SCLK_MACPLL 153 #define SCLK_SFC 160 /* aclk gates */ -- 1.9.1