Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755314AbcCPQGY (ORCPT ); Wed, 16 Mar 2016 12:06:24 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:35722 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932369AbcCPQGT (ORCPT ); Wed, 16 Mar 2016 12:06:19 -0400 From: Vishnu Patekar To: robh+dt@kernel.org, corbet@lwn.net, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, maxime.ripard@free-electrons.com, linux@arm.linux.org.uk, emilio@elopez.com.ar Cc: jenskuske@gmail.com, hdegoede@redhat.com, wens@csie.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, mturquette@baylibre.com, sboyd@codeaurora.org, patchesrdh@mveas.com, linux-clk@vger.kernel.org Subject: [PATCH v4 05/13] ARM: dts: sun8i-a83t: add mmc clock nodes Date: Thu, 17 Mar 2016 00:04:28 +0800 Message-Id: <1458144276-31108-6-git-send-email-vishnupatekar0510@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1458144276-31108-1-git-send-email-vishnupatekar0510@gmail.com> References: <1458144276-31108-1-git-send-email-vishnupatekar0510@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1390 Lines: 52 mmc clocks are compatible with that of earlier sun8i socs. This adds mmc0, mmc1, and mmc2 clock nodes for A83T. Signed-off-by: Vishnu Patekar Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a83t.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 2689af4..943d8a8 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -237,6 +237,36 @@ "bus_uart2", "bus_uart3", "bus_uart4"; }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc0", + "mmc0_output", + "mmc0_sample"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc1", + "mmc1_output", + "mmc1_sample"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc2", + "mmc2_output", + "mmc2_sample"; + }; }; soc { -- 1.9.1