Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031191AbcCQQ1Q (ORCPT ); Thu, 17 Mar 2016 12:27:16 -0400 Received: from mail-pf0-f173.google.com ([209.85.192.173]:33183 "EHLO mail-pf0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936285AbcCQQ1K (ORCPT ); Thu, 17 Mar 2016 12:27:10 -0400 From: Magnus Damm To: iommu@lists.linux-foundation.org Cc: laurent.pinchart+renesas@ideasonboard.com, geert+renesas@glider.be, joro@8bytes.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, horms+renesas@verge.net.au, Magnus Damm Date: Fri, 18 Mar 2016 01:30:32 +0900 Message-Id: <20160317163032.24104.7820.sendpatchset@little-apple> In-Reply-To: <20160317162909.24104.31682.sendpatchset@little-apple> References: <20160317162909.24104.31682.sendpatchset@little-apple> Subject: [PATCH 09/10] iommu/ipmmu-vmsa: Allow two bit SL0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1947 Lines: 65 From: Magnus Damm Introduce support for two bit SL0 bitfield in IMTTBCR by using a separate feature flag. Signed-off-by: Magnus Damm --- drivers/iommu/ipmmu-vmsa.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) --- 0025/drivers/iommu/ipmmu-vmsa.c +++ work/drivers/iommu/ipmmu-vmsa.c 2016-03-18 00:33:36.500513000 +0900 @@ -37,6 +37,7 @@ struct ipmmu_features { bool use_ns_alias_offset; bool has_cache_leaf_nodes; bool setup_imbuscr; + bool twobit_imttbcr_sl0; }; struct ipmmu_vmsa_device { @@ -141,6 +142,10 @@ static struct ipmmu_vmsa_domain *to_vmsa #define IMTTBCR_TSZ0_MASK (7 << 0) #define IMTTBCR_TSZ0_SHIFT O +#define IMTTBCR_SL0_TWOBIT_LVL_3 (0 << 6) +#define IMTTBCR_SL0_TWOBIT_LVL_2 (1 << 6) +#define IMTTBCR_SL0_TWOBIT_LVL_1 (2 << 6) + #define IMBUSCR 0x000c #define IMBUSCR_DVM (1 << 2) #define IMBUSCR_BUSSEL_SYS (0 << 0) @@ -356,6 +361,7 @@ static struct iommu_gather_ops ipmmu_gat static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain) { u64 ttbr; + u32 tmp; int ret; /* @@ -408,9 +414,15 @@ static int ipmmu_domain_init_context(str * We use long descriptors with inner-shareable WBWA tables and allocate * the whole 32-bit VA space to TTBR0. */ + + if (domain->root->features->twobit_imttbcr_sl0) + tmp = IMTTBCR_SL0_TWOBIT_LVL_1; + else + tmp = IMTTBCR_SL0_LVL_1; + ipmmu_ctx_write(domain, IMTTBCR, IMTTBCR_EAE | IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA | - IMTTBCR_IRGN0_WB_WA | IMTTBCR_SL0_LVL_1); + IMTTBCR_IRGN0_WB_WA | tmp); /* MAIR0 */ ipmmu_ctx_write(domain, IMMAIR0, domain->cfg.arm_lpae_s1_cfg.mair[0]); @@ -994,6 +1006,7 @@ static const struct ipmmu_features ipmmu .use_ns_alias_offset = true, .has_cache_leaf_nodes = false, .setup_imbuscr = true, + .twobit_imttbcr_sl0 = false, }; static const struct of_device_id ipmmu_of_ids[] = {