From: Yunhui Cui <yunhui.cui@nxp.com>
To: =?gb2312?B?QmVhbiBIdW8gu/Sx87HzIChiZWFuaHVvKQ==?= 
	<beanhuo@micron.com>,
        Yunhui Cui <B56489@freescale.com>
CC: "linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
        "dwmw2@infradead.org" <dwmw2@infradead.org>,
        "computersforpeace@gmail.com" <computersforpeace@gmail.com>,
        "han.xu@freescale.com" <han.xu@freescale.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
        "linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
        Yao Yuan <yao.yuan@nxp.com>
Subject: RE: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection
Thread-Topic: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection
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Date: Fri, 18 Mar 2016 10:08:58 +0000
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Hi Bean,

Thanks for your suggestions very much.
Yes, the flash N25Q128A status register write enable/disable bit is disable in initial state.
But, This patch aims to clear status register bit[7](write enable/disable bit) to 0, which enables the bit.
Frankly speaking, I also don't want to add this patch.
The reason for this is that clear status register bit[7] to 0 is a must to set quad mode to Enhanced Volatile Configuration Register using command SPINOR_OP_WD_EVCR. Otherwise it will output "Micron EVCR Quad bit not clear" in spi-nor.c
I looked up the datasheet, but I really don't find out any connection between status register bit[7](write enable/disable bit) equals 0 and seting quad mode to Enhanced Volatile Configuration Register.

Just as I want to send the issue to Micron team , could you give me some solutions ?


Thanks 
Yunhui

-----Original Message-----
From: Bean Huo ?????? (beanhuo) [mailto:beanhuo@micron.com] 
Sent: Thursday, March 03, 2016 9:39 PM
To: Yunhui Cui
Cc: linux-mtd@lists.infradead.org; dwmw2@infradead.org; computersforpeace@gmail.com; han.xu@freescale.com; linux-kernel@vger.kernel.org; linux-mtd@lists.infradead.org; linux-arm-kernel@lists.infradead.org; Yao Yuan; Yunhui Cui
Subject: Re: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection

> From: Yunhui Cui <B56489@freescale.com>
> To: <dwmw2@infradead.org>, <computersforpeace@gmail.com>,
> 	<han.xu@freescale.com>
> Cc: <linux-kernel@vger.kernel.org>, <linux-mtd@lists.infradead.org>,
> 	<linux-arm-kernel@lists.infradead.org>, <yao.yuan@nxp.com>, Yunhui 
> Cui
> 	<yunhui.cui@nxp.com>
> Subject: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW
> 	protection
> Message-ID: <1456988044-37061-4-git-send-email-B56489@freescale.com>
> Content-Type: text/plain
> 
> From: Yunhui Cui <yunhui.cui@nxp.com>
> 
> For Micron family ,The status register write enable/disable bit, 
> provides hardware data protection for the device.
> When the enable/disable bit is set to 1, the status register 
> nonvolatile bits become read-only and the WRITE STATUS REGISTER 
> operation will not execute.
> 
> Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
> ---
>  drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c 
> b/drivers/mtd/spi-nor/spi-nor.c index ed0c19c..917f814 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -39,6 +39,7 @@
> 
>  #define SPI_NOR_MAX_ID_LEN	6
>  #define SPI_NOR_MAX_ADDR_WIDTH	4
> +#define SPI_NOR_MICRON_WRITE_ENABLE	0x7f
> 
>  struct flash_info {
>  	char		*name;
> @@ -1238,6 +1239,14 @@ int spi_nor_scan(struct spi_nor *nor, const 
> char *name, enum read_mode mode)
>  		write_sr(nor, 0);
>  	}
> 
> +	if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
> +		ret = read_sr(nor);
> +		ret &= SPI_NOR_MICRON_WRITE_ENABLE;
> +
For Micron the status register write enable/disable bit, its default/factory value is disable.
Can here first check ,then program?
> +		write_enable(nor);
> +		write_sr(nor, ret);
> +	}
> +
>  	if (!mtd->name)
>  		mtd->name = dev_name(dev);
>  	mtd->priv = nor;