Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752626AbcCSHoP (ORCPT ); Sat, 19 Mar 2016 03:44:15 -0400 Received: from 212-186-180-163.dynamic.surfer.at ([212.186.180.163]:47975 "EHLO cgate.sperl.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752364AbcCSHoO convert rfc822-to-8bit (ORCPT ); Sat, 19 Mar 2016 03:44:14 -0400 Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 8.2 \(2104\)) Subject: Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835" From: Martin Sperl In-Reply-To: <87fuvn1a9p.fsf@eliezer.anholt.net> Date: Sat, 19 Mar 2016 08:44:09 +0100 Cc: Stefan Wahren , John Youn , Doug Anderson , Michael Niewoehner , Tao Huang , Julius Werner , Greg Kroah-Hartman , "linux-kernel@vger.kernel.org" , "linux-usb@vger.kernel.org" , Caesar Wang , Heiko Stuebner , Felipe Balbi , Remi Pommarel Content-Transfer-Encoding: 8BIT Message-Id: <8E14A795-8C35-4C4D-8D3A-09F29EE42A5F@martin.sperl.org> References: <1457115786-11370-1-git-send-email-dianders@chromium.org> <1457115786-11370-2-git-send-email-dianders@chromium.org> <1400647253.149212.b3bb45b6-c852-4cf1-9d3e-9fb299176369.open-xchange@email.1und1.de> <941828343.8833.cdbd40c7-e6f4-4b3e-9665-30fc6680f6e0.open-xchange@email.1und1.de> <56E1C79D.3090104@synopsys.com> <56E9A5E8.7090102@synopsys.com> <1440674775.86542.7bdab192-0ed1-49f2-8559-819af7131cbd.open-xchange@email.1und1.de> <87fuvn1a9p.fsf@eliezer.anholt.net> To: Eric Anholt X-Mailer: Apple Mail (2.2104) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1273 Lines: 37 > On 19.03.2016, at 03:17, Eric Anholt wrote: > > Stefan Wahren writes: > >> Hi Eric, >> hi Martin, >> >>> John Youn hat am 16. März 2016 um 19:28 geschrieben: >>> >>> >>> On 3/10/2016 11:14 AM, John Youn wrote: >>>> On 3/9/2016 11:06 AM, Doug Anderson wrote: >>>>> >>>>> John: it's pretty clear that there's something taking almost exactly >>>>> 10ms on my system and almost exactly 50ms on Stefan's system. Is >>>>> there some register we could poll to see when this process is done? >>>>> ...or can we look at the dwc2 revision number / feature register and >>>>> detect how long to delay? >>>>> Maybe this difference is related to overclocking settings in the firmware? >>> >>> 1. What is the AHB Clock frequency? Is the AHB Clock gated during >>> Reset? > > Low confidence here as I'm tracing lines across a ton of modules, but it > looks like it comes from the USB AXI clock in peri_image, which is a > gate on the normal 250Mhz APB clock, but nothing should be touching that > gate register as part of USB reset as far as I know. > Isn’t it possible that this clock (probably BCM2835_CLOCK_VPU) is changed by the firmware due to overclocking settings in /boot/config.txt? Martin