Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757006AbcCUP6q (ORCPT ); Mon, 21 Mar 2016 11:58:46 -0400 Received: from mail-bn1on0087.outbound.protection.outlook.com ([157.56.110.87]:4832 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1756639AbcCUP62 (ORCPT ); Mon, 21 Mar 2016 11:58:28 -0400 Authentication-Results: spf=fail (sender IP is 66.35.236.236) smtp.mailfrom=opensource.altera.com; vger.kernel.org; dkim=pass (signature was verified) header.d=altera.onmicrosoft.com;vger.kernel.org; dmarc=none action=none header.from=opensource.altera.com; Authentication-Results: alien8.de; dkim=none (message not signed) header.d=none;alien8.de; dmarc=none action=none header.from=opensource.altera.com; From: To: , , , , , , , , , , CC: , , , , , , Subject: [PATCHv3 6/9] Documentation: dt: socfpga: Add Altera Arria10 L2 cache binding Date: Mon, 21 Mar 2016 11:01:43 -0500 Message-ID: <1458576106-24505-7-git-send-email-tthayer@opensource.altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1458576106-24505-1-git-send-email-tthayer@opensource.altera.com> References: <1458576106-24505-1-git-send-email-tthayer@opensource.altera.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: CY1PR0601CA0028.namprd06.prod.outlook.com (25.160.162.38) To BY1PR03MB1481.namprd03.prod.outlook.com (25.162.210.14) X-MS-Office365-Filtering-Correlation-Id: e2979b90-b5cc-41bf-f6e9-08d351a1a227 X-Microsoft-Exchange-Diagnostics-untrusted: 1;BY1PR03MB1481;2:iHrIUDiygOVko+6lO9y0BBf0Y0i6dhZ9k8loRwwPVQTs0zsTKgibUO3IZltadntgcSo659oZE11G4FBmvpd5eGKzYkRHkc8p/4AkTy1hNpVY0odWWz4Kh6itywILd7lJ1aNf6SouMxjXoht27TWPcJa3kGsX630EAmQUCH31YcWqps+99GnQvGpjeSZCl8wY;3:yabI+h8XkplQn5lt7xgqHLsG7i1Bgi6rkt7NCsF1ROnHShdVb1id2wngP4lasK0xcV80nu7z0a3DpRdDiM1GVaL13y3YPZnHe9dTEWwj3ZGiITIWSb/szueEZViiAiFz;25:CirTjsolj/iiBST/3YyF+E9BEA7/xPD+d2vUknQT3zyuBSH+bJrn0TLNawirs44IQg2CsBPjZwJNnN0yoljN9w8WEZxP+1iEi+7kOjm407gMcGg4GMCkjkAsFOm1E/eJNlijrID/nHJDbD1VYFSFG+3HUAx+Oktnk2pCkz8Yp6elCU3lHz9m5rZmnUG8hnoQgyqcwBib5gpFbgzu/ZufGIheUXnJ75E0ZYLtr/4jTXhLxI0RjKId5tukH0K1KM9/45whrQ8EUc0ZMYu+8ePUC5qn0RPyMLJ2a5fxyqzJ3chCmZ2Z3CIbs+p2VSrXRtBolEj2t2tVqaGrn8h8EWpp780/aGzCX7820C34XaZZ48NPXMu4JXpAhnO8GrNglLi73DRZCSvNZ3AnkEGGCbhNSSZ/K1Q717encX3rK/84hDbVtLcJfYvUGL5A88hqqQn4wbSQQdXn8aFEYqfJfXEH9YBgJRThC0Wmvyjsml2Ck7VnMrd4XBFCUZBUAdKfW2V3 X-Microsoft-Antispam-Untrusted: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY1PR03MB1481; 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Since all the peripherals share IRQs, the IRQ fields are now in the ecc_manager. Signed-off-by: Thor Thayer --- v2 Correct spelling of Arria10 in patch title. v3 Major restructuring change for ecc_manager to include IRQs --- .../bindings/arm/altera/socfpga-eccmgr.txt | 40 ++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt index 885f93d..37ff9bf 100644 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt @@ -3,6 +3,7 @@ This driver uses the EDAC framework to implement the SOCFPGA ECC Manager. The ECC Manager counts and corrects single bit errors and counts/handles double bit errors which are uncorrectable. +Cyclone5 and Arria5 ECC Manager Required Properties: - compatible : Should be "altr,socfpga-ecc-manager" - #address-cells: must be 1 @@ -47,3 +48,42 @@ Example: interrupts = <0 178 1>, <0 179 1>; }; }; + +Arria10 SoCFPGA ECC Manager +The Arria10 SoC ECC Manager handles the IRQs for each peripheral +in a shared register instead of individual IRQs like the Cyclone5 +and Arria5. Therefore the device tree is different as well. + +Required Properties: +- compatible : Should be "altr,socfpga-a10-ecc-manager" +- altr,sysgr-syscon : phandle to Arria10 System Manager Block + containing the ECC manager registers. +- #address-cells: must be 1 +- #size-cells: must be 1 +- interrupts : Should be single bit error interrupt, then double bit error + interrupt. Note the rising edge type. +- ranges : standard definition, should translate from local addresses + +Subcomponents: + +L2 Cache ECC +Required Properties: +- compatible : Should be "altr,socfpga-a10-l2-ecc" +- reg : Address and size for ECC error interrupt clear registers. + +Example: + + eccmgr: eccmgr@ffd06000 { + compatible = "altr,socfpga-a10-ecc-manager"; + altr,sysmgr-syscon = <&sysmgr>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 0 IRQ_TYPE_LEVEL_HIGH>; + ranges; + + l2-ecc@ffd06010 { + compatible = "altr,socfpga-a10-l2-ecc"; + reg = <0xffd06010 0x4>; + }; + }; -- 1.7.9.5