Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758894AbcCVLCK (ORCPT ); Tue, 22 Mar 2016 07:02:10 -0400 Received: from mail-oi0-f42.google.com ([209.85.218.42]:35259 "EHLO mail-oi0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758816AbcCVLCA (ORCPT ); Tue, 22 Mar 2016 07:02:00 -0400 MIME-Version: 1.0 In-Reply-To: <1457108379-20794-1-git-send-email-thierry.reding@gmail.com> References: <1457108379-20794-1-git-send-email-thierry.reding@gmail.com> Date: Tue, 22 Mar 2016 12:01:58 +0100 Message-ID: Subject: Re: [PATCH v10 1/9] dt-bindings: phy: Add NVIDIA Tegra XUSB pad controller binding From: Linus Walleij To: Thierry Reding Cc: Kishon Vijay Abraham I , Stephen Warren , Alexandre Courbot , Andrew Bresticker , "linux-tegra@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-usb@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 788 Lines: 23 On Fri, Mar 4, 2016 at 5:19 PM, Thierry Reding wrote: > From: Thierry Reding > > The NVIDIA Tegra XUSB pad controller provides a set of pads, each with a > set of lanes that are used for PCIe, SATA and USB. > > Signed-off-by: Thierry Reding > --- > Changes in v10: > - clarify that the hardware documentation means something different when > referring to a "port" (intra-SoC connectivity) Thierry I'm a bit out of sync, so can you resend these patches with collected ACKs after -rc1? Please send me the patches I can just merge into the pinctrl tree separately if possible, I encourage any DTS changes to go in orthogonally through ARM SoC. The DTS business I regard as kind of its own tree. Yours, Linus Walleij