Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754473AbcCWJS1 (ORCPT ); Wed, 23 Mar 2016 05:18:27 -0400 Received: from webbox1416.server-home.net ([77.236.96.61]:37172 "EHLO webbox1416.server-home.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753964AbcCWJSU (ORCPT ); Wed, 23 Mar 2016 05:18:20 -0400 From: Alexander Stein To: linux-kernel@vger.kernel.org Cc: Minghuan Lian , linux-arm-kernel@lists.infradead.org, Marc Zyngier , Thomas Gleixner , Jason Cooper , Roy Zang , Mingkai Hu , Stuart Yoder , Yang-Leo Li Subject: Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support Date: Wed, 23 Mar 2016 10:18:11 +0100 Message-ID: <7239962.9Fyo0vfqsc@ws-stein> User-Agent: KMail/4.14.10 (Linux/4.1.15-gentoo-r1; KDE/4.14.16; x86_64; ; ) In-Reply-To: <1457321782-3245-2-git-send-email-Minghuan.Lian@nxp.com> References: <1457321782-3245-1-git-send-email-Minghuan.Lian@nxp.com> <1457321782-3245-2-git-send-email-Minghuan.Lian@nxp.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 731 Lines: 19 On Monday 07 March 2016 11:36:22, Minghuan Lian wrote: > Some kind of NXP Layerscape SoC provides a MSI > implementation which uses two SCFG registers MSIIR and > MSIR to support 32 MSI interrupts for each PCIe controller. > The patch is to support it. > > Signed-off-by: Minghuan Lian Tested-by: Alexander Stein Using an intel e1000e card which uses 3 MSIs. But the IRQ numbers are a bit strange though: > grep eth3 /proc/interrupts > > 63: 49 0 MSI 134742016 Edge eth3-rx-0 > 64: 3 0 MSI 134742017 Edge eth3-tx-0 > 65: 4 0 MSI 134742018 Edge eth3 Best regards, Alexander