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Subject: Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller
 support
To: Alexander Stein <alexander.stein@systec-electronic.com>,
        linux-kernel@vger.kernel.org
References: <1457321782-3245-1-git-send-email-Minghuan.Lian@nxp.com>
 <1457321782-3245-2-git-send-email-Minghuan.Lian@nxp.com>
 <7239962.9Fyo0vfqsc@ws-stein>
Cc: Minghuan Lian <Minghuan.Lian@nxp.com>,
        linux-arm-kernel@lists.infradead.org,
        Thomas Gleixner <tglx@linutronix.de>,
        Jason Cooper <jason@lakedaemon.net>, Roy Zang <roy.zang@nxp.com>,
        Mingkai Hu <mingkai.hu@nxp.com>, Stuart Yoder <stuart.yoder@nxp.com>,
        Yang-Leo Li <leoyang.li@nxp.com>
From: Marc Zyngier <marc.zyngier@arm.com>
Organization: ARM Ltd
Message-ID: <56F27914.3080908@arm.com>
Date: Wed, 23 Mar 2016 11:08:04 +0000
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On 23/03/16 09:18, Alexander Stein wrote:
> On Monday 07 March 2016 11:36:22, Minghuan Lian wrote:
>> Some kind of NXP Layerscape SoC provides a MSI
>> implementation which uses two SCFG registers MSIIR and
>> MSIR to support 32 MSI interrupts for each PCIe controller.
>> The patch is to support it.
>>
>> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> 
> Tested-by: Alexander Stein <alexander.stein@systec-electronic.com>
> 
> Using an intel e1000e card which uses 3 MSIs. But the IRQ numbers are a bit strange though:
>> grep eth3 /proc/interrupts
>>
>>  63:         49          0       MSI 134742016 Edge      eth3-rx-0
>>  64:          3          0       MSI 134742017 Edge      eth3-tx-0
>>  65:          4          0       MSI 134742018 Edge      eth3

This is a virtual interrupt number (despite being displayed as a hwirq),
computed from the PCI requester ID and the MSI index. You shouldn't
infer anything from it.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...