From: Alexander Stein <alexander.stein@systec-electronic.com>
To: Mark Brown <broonie@kernel.org>
Cc: linux-kernel@vger.kernel.org
Subject: Re: regmap: mmio: regression in pre-v4.6-rc1
Date: Wed, 23 Mar 2016 12:16:13 +0100
Message-ID: <4116114.XWfjkrStv7@ws-stein>
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On Wednesday 23 March 2016 10:34:15, Mark Brown wrote:
> > I'm currently trying to get PCIe working on LS1021A (little-endian
> > ARM). For link-detection I need access to a syscon perpheral (SCFG)
> > which is attched to CPU as big-endian.
> 
> Are you *sure* that this is actually big endian?  Are you basing this on
> documentation or on what happened to work for you in the past.

Please refer to QorIQ LS1021A Reference Manual (REV 0) table 2.2 (CCSR block 
base address map) which states that this peripheral (among _most_ but not all) 
requires byte swapping. Same for DSPI.
Yeah, it sounds strange.

> > Based on current linus's master (a24e3d414e59ac765, "Merge branch
> > 'akpm' (patches from Andrew)") I noticed the access is actually done
> > as little-endian.  I could track it down to commit 922a9f936e40001f
> > ("regmap: mmio: Convert to regmap_bus and fix accessor usage").
> > Reverting it, the access is fine now and I get my PCIe link.
> 
> Have you tried tracing through the code to see what ends up happening to
> the I/O?  It should come out using your architecture's big endian
> accessors.

In regmap_mmio_gen_context ctx->reg_read is set to regmap_mmio_read32le and 
ctx->reg_write to regmap_mmio_write32le respectively.

I noticed that before that change map->reg_read = _regmap_bus_read and map-
>reg_write = _regmap_bus_raw_write. After that change it is map->reg_read = 
_regmap_bus_reg_read resp. map->reg_write = _regmap_bus_reg_write.
I hope this description is not that confusing.

Best regards,
Alexander