Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754637AbcCWLjy (ORCPT ); Wed, 23 Mar 2016 07:39:54 -0400 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:57780 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751929AbcCWLjp (ORCPT ); Wed, 23 Mar 2016 07:39:45 -0400 Date: Wed, 23 Mar 2016 11:39:39 +0000 From: Mark Brown To: Alexander Stein Cc: linux-kernel@vger.kernel.org Message-ID: <20160323113939.GI2566@sirena.org.uk> References: <1981840.HVGTg07J9M@ws-stein> <20160323103415.GG2566@sirena.org.uk> <4116114.XWfjkrStv7@ws-stein> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="a86Iq1BtUPQA9xjr" Content-Disposition: inline In-Reply-To: <4116114.XWfjkrStv7@ws-stein> X-Cookie: Walk softly and carry a megawatt laser. User-Agent: Mutt/1.5.24 (2015-08-30) X-SA-Exim-Connect-IP: 2a01:348:6:8808:fab::3 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Re: regmap: mmio: regression in pre-v4.6-rc1 X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1716 Lines: 49 --a86Iq1BtUPQA9xjr Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Mar 23, 2016 at 12:16:13PM +0100, Alexander Stein wrote: > On Wednesday 23 March 2016 10:34:15, Mark Brown wrote: > > Are you *sure* that this is actually big endian? Are you basing this on > > documentation or on what happened to work for you in the past. > Please refer to QorIQ LS1021A Reference Manual (REV 0) table 2.2 (CCSR bl= ock=20 > base address map) which states that this peripheral (among _most_ but not= all)=20 > requires byte swapping. Same for DSPI. > Yeah, it sounds strange. I don't have that document. > > Have you tried tracing through the code to see what ends up happening to > > the I/O? It should come out using your architecture's big endian > > accessors. > In regmap_mmio_gen_context ctx->reg_read is set to regmap_mmio_read32le a= nd=20 > ctx->reg_write to regmap_mmio_write32le respectively. So how does that happen then? We set these values if the bus is default, little or native endian but if it's big endian we go into a completely different case... --a86Iq1BtUPQA9xjr Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBCAAGBQJW8oB6AAoJECTWi3JdVIfQMzYH/2REfX34o6jpzX5Et9pPMexE hFalLyYyWA9kxsb1B3NAQbdE//AfVMVJF44v+dO5klBFKb+wjOppHdx/iuUVWjIM EpJtSwtp2OW1y8c9lpdzBK9ywrisGdOzPx9k2/MAda4D8H9kGRv+LsjGI6rbk1kV u2hf4pckX4EgQXbf8Ppt/rLIM2CRuDjJo+zgDFlDssQ0Pt4nRSpZshj8cIEyQxR5 2VdWJMJRA3p+MkkNgVXCsX+x3ka2S1VB0AzVwmdEm0LeP+mKbZtDGEx40Jro2pW/ dnrjks82adNTd+SR4sRO/0Q/1HdmQDVHSdq9uRoqGVWcpAFUArB5gFizuSOo5h0= =ap3g -----END PGP SIGNATURE----- --a86Iq1BtUPQA9xjr--