Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755388AbcCWMtn (ORCPT ); Wed, 23 Mar 2016 08:49:43 -0400 Received: from eusmtp01.atmel.com ([212.144.249.243]:14227 "EHLO eusmtp01.atmel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755335AbcCWMtd (ORCPT ); Wed, 23 Mar 2016 08:49:33 -0400 From: Cyrille Pitchen To: , CC: , , , , , , , , , , Cyrille Pitchen Subject: [PATCH v3 2/2] doc: dt: mtd: add a DT property to enable the use of 4byte-address op codes Date: Wed, 23 Mar 2016 13:49:11 +0100 Message-ID: <93b32638d08044de4907b46b2e4a21c645298a48.1458736784.git.cyrille.pitchen@atmel.com> X-Mailer: git-send-email 1.8.2.2 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2037 Lines: 41 This patch adds a new optional DT property which enables an alternative way of supporting memory size above 16MiB (128Mib). This new mechanism translates the regular 3byte-address op codes into their 4byte-address version whereas the old/default mecanism makes the SPI memory enter its 4byte-address mode, which has annoying side effects for early bootloaders. We cannot discover at run time whether the SPI NOR memory supports the 4byte-address op codes. For instance both Macronix MX25L25635E and MX25L25673G share the same JEDEC ID (C22019 without any extension byte). However the first one doesn't support 4byte-address op codes whereas the second one does. Signed-off-by: Cyrille Pitchen --- Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt index 2c91c03e7eb0..8be610482089 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt @@ -66,6 +66,17 @@ Optional properties: Refer to your chips' datasheet to check if this is supported by your chip. +- m25p,4byte-opcodes: For memory size above 16MiB (128Mib), use the dedicated + 4byte-address opcodes instead of entering the 4byte + address mode. This mode changes the internal state of the + chip so may conflict with some early boot loaders, which + expect to use the regular (Fast) Read opcodes with 3byte + address. + However 4byte-address opcodes are not supported by all + chips and support for them can not be detected at runtime. + Refer to you chip's datasheet to check if this is + supported by your chip. + Example: flash: m25p80@0 { -- 1.8.2.2