Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755257AbcCXLsx (ORCPT ); Thu, 24 Mar 2016 07:48:53 -0400 Received: from mailout3.w1.samsung.com ([210.118.77.13]:42762 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750926AbcCXLso (ORCPT ); Thu, 24 Mar 2016 07:48:44 -0400 X-AuditID: cbfec7f5-f792a6d000001302-60-56f3d4184bbd Subject: Re: [PATCH 2/3] phy: exynos-mipi-video: Rewrite handling of phy registers To: Marek Szyprowski References: <1458731358-773-1-git-send-email-m.szyprowski@samsung.com> <1458731358-773-3-git-send-email-m.szyprowski@samsung.com> Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, Kishon Vijay Abraham I , Inki Dae , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz From: Sylwester Nawrocki Message-id: <56F3D416.3070701@samsung.com> Date: Thu, 24 Mar 2016 12:48:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-version: 1.0 In-reply-to: <1458731358-773-3-git-send-email-m.szyprowski@samsung.com> Content-type: text/plain; charset=windows-1252 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrPLMWRmVeSWpSXmKPExsVy+t/xq7oSVz6HGcxqZLPYOGM9q8Wk+xNY LF6/MLS48LSHzeLyrjlsFjPO72OyWHvkLrsDu0ffllWMHsdvbGfy+LxJLoA5issmJTUnsyy1 SN8ugStjzxz3gja2ipcPOpkaGH+ydDFyckgImEic3r6aFcIWk7hwbz1bFyMXh5DAUkaJhxMe MkI4zxkljk8+D1YlLBAisfPICXYQW0RAX6K77QojiC0k0MwocX2mM0gDs8B3RonNv56DrWAT MJToPdoHVsQroCXxafVrZhCbRUBV4u6fvWwgtqhAhMSTuSehagQlfky+B9bLKeAu0bDsLZDN ATRUT+L+RS2QMLOAvMTmNW+ZJzAKzELSMQuhahaSqgWMzKsYRVNLkwuKk9JzjfSKE3OLS/PS 9ZLzczcxQoL56w7GpcesDjEKcDAq8fDe4PocJsSaWFZcmXuIUYKDWUmE988JoBBvSmJlVWpR fnxRaU5q8SFGaQ4WJXHembvehwgJpCeWpGanphakFsFkmTg4pRoYpbKZZs/vPVCyQO+i/Qv1 jJ2cr38/fbMpj31p9JsN/6R+9U9LPGi6UUvJUDhblMV68sX/SxJ5n9R0mzV6nlmWIzU9WCBJ hpdJ7csXxq91j6I6FZOjJjGvfxSj/atSPGf/n11WcddC5z9OvFH9MvbfG7MzIZJltVuvxZT6 vmDq+lb2SvNlauo5JZbijERDLeai4kQA9NB8uWICAAA= Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 755 Lines: 19 On 03/23/2016 12:09 PM, Marek Szyprowski wrote: > Controlling Exynos MIPI DPHY is done by handling 2 registers: one for > phy reset and one for enabling it. This patch moves definitions of those > 2 registers to speparate exynos_mipi_phy_desc structure, which can be > defined separately for each PHY for each supported hardware variant. > This code rewrite is needed to add support for newer Exynos SoCs, which > have MIPI PHY related registers at different offsets or even different > register regions. > > Signed-off-by: Marek Szyprowski I've tested this patch series on Trats2 and an exynos5433 based board and it seems to be all working well. Acked-by: Sylwester Nawrocki -- Thanks, Sylwester