Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758112AbcCXQwr (ORCPT ); Thu, 24 Mar 2016 12:52:47 -0400 Received: from mail-wm0-f45.google.com ([74.125.82.45]:34304 "EHLO mail-wm0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757457AbcCXQux (ORCPT ); Thu, 24 Mar 2016 12:50:53 -0400 From: Neil Armstrong To: linux-kernel@vger.kernel.org, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org, linus.walleij@linaro.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Neil Armstrong Subject: [PATCH v3 12/18] dt-bindings: Add PLX Technology OXNAS pinctrl and gpio bindings Date: Thu, 24 Mar 2016 17:50:09 +0100 Message-Id: <1458838215-23314-13-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1458838215-23314-1-git-send-email-narmstrong@baylibre.com> References: <1458838215-23314-1-git-send-email-narmstrong@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4098 Lines: 129 Add pinctrl and gpio DT bindings for PLX Technology OXNAS SoC Family. This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins. Signed-off-by: Neil Armstrong --- .../devicetree/bindings/gpio/gpio_oxnas.txt | 47 ++++++++++++++++++ .../bindings/pinctrl/plxtech,pinctrl.txt | 57 ++++++++++++++++++++++ 2 files changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio_oxnas.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt diff --git a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt new file mode 100644 index 0000000..4530fa9 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt @@ -0,0 +1,47 @@ +* PLX Technology OXNAS SoC GPIO Controller + +Required properties: + - compatible: "oxsemi,ox810se-gpio" + - reg: Base address and length for the device. + - interrupts: The port interrupt shared by all pins. + - gpio-controller: Marks the port as GPIO controller. + - #gpio-cells: Two. The first cell is the pin number and + the second cell is used to specify the gpio polarity as defined in + defined in : + 0 = GPIO_ACTIVE_HIGH + 1 = GPIO_ACTIVE_LOW + - interrupt-controller: Marks the device node as an interrupt controller. + - #interrupt-cells: Two. The first cell is the GPIO number and second cell + is used to specify the trigger type as defined in + : + IRQ_TYPE_EDGE_RISING + IRQ_TYPE_EDGE_FALLING + IRQ_TYPE_EDGE_BOTH + - plxtech,gpio-bank: Specifies which bank a controller owns. + - gpio-ranges: Interaction with the PINCTRL subsystem. + - ngpios: Specifies the gpio lines count in this specific bank. + +Example: + +gpio0: gpio@0 { + compatible = "oxsemi,ox810se-gpio"; + reg = <0x000000 0x100000>; + interrupts = <21>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + plxtech,gpio-bank = <0>; + gpio-ranges = <&pinctrl 0 0 32>; + ngpios = <32>; +}; + +keys { + ... + + button@sw1 { + label = "ESC"; + linux,code = <1>; + gpios = <&gpio0 12 0>; + }; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt new file mode 100644 index 0000000..dc4907b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt @@ -0,0 +1,57 @@ +* PLX Technology OXNAS SoC Family Pin Controller + +Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and +../interrupt-controller/interrupts.txt for generic information regarding +pin controller, GPIO, and interrupt bindings. + +OXNAS 'pin configuration node' is a node of a group of pins which can be +used for a specific device or function. This node represents configurations of +pins, optional function, and optional mux related configuration. + +Required properties for pin controller node: + - compatible: "oxsemi,ox810se-pinctrl" + - plxtech,sys-ctrl: a phandle to the system controller syscon node + +Required properties for pin configuration sub-nodes: + - pins: List of pins to which the configuration applies. + +Optional properties for pin configuration sub-nodes: +---------------------------------------------------- + - function: Mux function for the specified pins. + - bias-pull-up: Enable weak pull-up. + +Example: + +pinctrl: pinctrl { + compatible = "oxsemi,ox810se-pinctrl"; + + /* Regmap for sys registers */ + plxtech,sys-ctrl = <&sys>; + + pinctrl_uart2: pinctrl_uart2 { + uart2a { + pins = "gpio31"; + function = "fct3"; + }; + uart2b { + pins = "gpio32"; + function = "fct3"; + }; + }; +}; + +uart2: serial@900000 { + compatible = "ns16550a"; + reg = <0x900000 0x100000>; + clocks = <&sysclk>; + interrupts = <29>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; -- 1.9.1