Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754591AbcCYVbS (ORCPT ); Fri, 25 Mar 2016 17:31:18 -0400 Received: from mail-pf0-f182.google.com ([209.85.192.182]:36583 "EHLO mail-pf0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754205AbcCYVbP (ORCPT ); Fri, 25 Mar 2016 17:31:15 -0400 Date: Fri, 25 Mar 2016 14:31:12 -0700 From: Bjorn Andersson To: Matthew McClintock , linus.walleij@linaro.org Cc: andy.gross@linaro.org, linux-arm-msm@vger.kernel.org, qca-upstream.external@qca.qualcomm.com, Sricharan R , Rob Herring , Mathieu Olivari , Varadarajan Narayanan , "open list:PIN CONTROL SUBSYSTEM" , open list Subject: Re: [PATCH 03/17] pinctrl: qcom: ipq4019: fix register offsets Message-ID: <20160325213112.GC8929@tuxbot> References: <1458770712-10880-1-git-send-email-mmcclint@codeaurora.org> <1458770712-10880-4-git-send-email-mmcclint@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1458770712-10880-4-git-send-email-mmcclint@codeaurora.org> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1524 Lines: 45 On Wed 23 Mar 15:04 PDT 2016, Matthew McClintock wrote: > For this SoC the register offsets changed from previous versions to be > separated by a larger amount. > > CC: linus.walleij@linaro.org So the HW guys changed the register layout of the TLMM block? Matches the layout of contemporary MSMs, so I see no problems with this. Acked-by: bjorn.andersson@linaro.org Regards, Bjorn > Signed-off-by: Matthew McClintock > --- > drivers/pinctrl/qcom/pinctrl-ipq4019.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c > index cb9f16a..b68ae42 100644 > --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c > +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c > @@ -254,11 +254,11 @@ DECLARE_QCA_GPIO_PINS(99); > qca_mux_##f14 \ > }, \ > .nfuncs = 15, \ > - .ctl_reg = 0x1000 + 0x10 * id, \ > - .io_reg = 0x1004 + 0x10 * id, \ > - .intr_cfg_reg = 0x1008 + 0x10 * id, \ > - .intr_status_reg = 0x100c + 0x10 * id, \ > - .intr_target_reg = 0x400 + 0x4 * id, \ > + .ctl_reg = 0x0 + 0x1000 * id, \ > + .io_reg = 0x4 + 0x1000 * id, \ > + .intr_cfg_reg = 0x8 + 0x1000 * id, \ > + .intr_status_reg = 0xc + 0x1000 * id, \ > + .intr_target_reg = 0x8 + 0x1000 * id, \ > .mux_bit = 2, \ > .pull_bit = 0, \ > .drv_bit = 6, \ > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >