Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754768AbcC1SN7 (ORCPT ); Mon, 28 Mar 2016 14:13:59 -0400 Received: from bh-25.webhostbox.net ([208.91.199.152]:59556 "EHLO bh-25.webhostbox.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751156AbcC1SN4 (ORCPT ); Mon, 28 Mar 2016 14:13:56 -0400 Date: Mon, 28 Mar 2016 11:13:56 -0700 From: Guenter Roeck To: Matthew McClintock Cc: andy.gross@linaro.org, linux-arm-msm@vger.kernel.org, "qca-upstream.external" , Wim Van Sebroeck , "open list:WATCHDOG DEVICE DRIVERS" , open list Subject: Re: [PATCH 07/17] watchdog: qcom: add option for standalone watchdog not in timer block Message-ID: <20160328181356.GA29820@roeck-us.net> References: <1458770712-10880-1-git-send-email-mmcclint@codeaurora.org> <1458770712-10880-8-git-send-email-mmcclint@codeaurora.org> <20160325162326.GA25767@roeck-us.net> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) X-Authenticated_sender: guenter@roeck-us.net X-OutGoing-Spam-Status: No, score=-1.0 X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - bh-25.webhostbox.net X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - roeck-us.net X-Get-Message-Sender-Via: bh-25.webhostbox.net: authenticated_id: guenter@roeck-us.net X-Authenticated-Sender: bh-25.webhostbox.net: guenter@roeck-us.net X-Source: X-Source-Args: X-Source-Dir: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2058 Lines: 52 On Mon, Mar 28, 2016 at 11:55:28AM -0500, Matthew McClintock wrote: > > > On Mar 25, 2016, at 11:23 AM, Guenter Roeck wrote: > > > >> -#define WDT_RST 0x38 > >> -#define WDT_EN 0x40 > >> -#define WDT_BITE_TIME 0x5C > >> +enum wdt_reg { > >> + WDT_RST, > >> + WDT_EN, > >> + WDT_BITE_TIME, > >> +}; > >> + > >> +static const u32 reg_offset_data_apcs_tmr[] = { > >> + [WDT_RST] = 0x38, > >> + [WDT_EN] = 0x40, > >> + [WDT_BITE_TIME] = 0x5C, > >> +}; > >> + > >> +static const u32 reg_offset_data_kpss[] = { > >> + [WDT_RST] = 0x4, > >> + [WDT_EN] = 0x8, > > > > Does this work ? In the datasheet I have in front of me (APQ8064), the watchdog > > at this address uses different bits. At address 0x40 (eg GSS_A5_APCS_WDT0_EN), > > 0x40 is acps_tmr, and looks fine. > > > bit 0 is the enable bit, and bit 1 enables interrupts. At address 0x08 (eg > > LPASS_QDSP6SS_WDOG_UNMASKED_INT_EN), bit 0 enables interrupts and bit 1 is > > undefined. > > I honestly don’t see anything at 0x8 for either blocks that looks like this. For the new block bit 0 is enabling and bit 1 enabled interrupts. > That is from the APQ8064 datasheet. > > Or does "qcom,kpss-standalone" refer to some other watchdog ? > > APQ8064 would be the apcs_tmr block variant which is unchanged. MSM8916 as well as IPQ4019 would use the new kpss variant. > Unfortunately I don't have access to those datasheets. > I went with block names I found internally here, but I will be the first to admit I am terrible at names. The old block name for APQ was CPU0_ACPS_TMR (where really the watchdog is a subset of a timer block), and on the IPQ4019 it’s called APCS_KPSS_WDT and it’s really just a watchdog block. > > I kept the same driver because the register’s currently in use were compatible. By the way, I tested this on an IPQ806x and IPQ4019 both new and old blocks. > The property name should probably be something like 'qcom,kpss-wdt' (or 'qcom,kpss-watchdog' ?), possibly in addition to 'qcom,kpss-ipq4019-wdt' and 'qcom,kpss-msm8916-wdt'. Guenter