Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755257AbcC1UlG (ORCPT ); Mon, 28 Mar 2016 16:41:06 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:46505 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751281AbcC1UlD convert rfc822-to-8bit (ORCPT ); Mon, 28 Mar 2016 16:41:03 -0400 Subject: Re: [PATCH 07/17] watchdog: qcom: add option for standalone watchdog not in timer block Mime-Version: 1.0 (Mac OS X Mail 9.2 \(3112\)) Content-Type: text/plain; charset=utf-8 From: Matthew McClintock In-Reply-To: <20160328181356.GA29820@roeck-us.net> Date: Mon, 28 Mar 2016 15:40:58 -0500 Cc: andy.gross@linaro.org, linux-arm-msm@vger.kernel.org, "qca-upstream.external" , Wim Van Sebroeck , "open list:WATCHDOG DEVICE DRIVERS" , open list Content-Transfer-Encoding: 8BIT Message-Id: <938942F3-D0ED-4BCA-9B6A-EF716A101E0C@codeaurora.org> References: <1458770712-10880-1-git-send-email-mmcclint@codeaurora.org> <1458770712-10880-8-git-send-email-mmcclint@codeaurora.org> <20160325162326.GA25767@roeck-us.net> <20160328181356.GA29820@roeck-us.net> To: Guenter Roeck X-Mailer: Apple Mail (2.3112) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 584 Lines: 15 On Mar 28, 2016, at 1:13 PM, Guenter Roeck wrote: > >>> bit 0 is the enable bit, and bit 1 enables interrupts. At address 0x08 (eg >>> LPASS_QDSP6SS_WDOG_UNMASKED_INT_EN), bit 0 enables interrupts and bit 1 is >>> undefined. >> >> I honestly don’t see anything at 0x8 for either blocks that looks like this. For the new block bit 0 is enabling and bit 1 enabled interrupts. >> > That is from the APQ8064 datasheet. So taken from the timer offset 0x0208A000 I just have a generic counter register CPU0_APCS_GPT0_CNT at 0x8 What doc are you looking at? -M