Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755360AbcC1V4n (ORCPT ); Mon, 28 Mar 2016 17:56:43 -0400 Received: from bh-25.webhostbox.net ([208.91.199.152]:47818 "EHLO bh-25.webhostbox.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752523AbcC1V4i (ORCPT ); Mon, 28 Mar 2016 17:56:38 -0400 Date: Mon, 28 Mar 2016 14:56:38 -0700 From: Guenter Roeck To: Matthew McClintock Cc: andy.gross@linaro.org, linux-arm-msm@vger.kernel.org, "qca-upstream.external" , Wim Van Sebroeck , "open list:WATCHDOG DEVICE DRIVERS" , open list Subject: Re: [PATCH 07/17] watchdog: qcom: add option for standalone watchdog not in timer block Message-ID: <20160328215638.GA25221@roeck-us.net> References: <1458770712-10880-1-git-send-email-mmcclint@codeaurora.org> <1458770712-10880-8-git-send-email-mmcclint@codeaurora.org> <20160325162326.GA25767@roeck-us.net> <20160328181356.GA29820@roeck-us.net> <938942F3-D0ED-4BCA-9B6A-EF716A101E0C@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <938942F3-D0ED-4BCA-9B6A-EF716A101E0C@codeaurora.org> User-Agent: Mutt/1.5.23 (2014-03-12) X-Authenticated_sender: guenter@roeck-us.net X-OutGoing-Spam-Status: No, score=-1.0 X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - bh-25.webhostbox.net X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - roeck-us.net X-Get-Message-Sender-Via: bh-25.webhostbox.net: authenticated_id: guenter@roeck-us.net X-Authenticated-Sender: bh-25.webhostbox.net: guenter@roeck-us.net X-Source: X-Source-Args: X-Source-Dir: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1083 Lines: 26 On Mon, Mar 28, 2016 at 03:40:58PM -0500, Matthew McClintock wrote: > On Mar 28, 2016, at 1:13 PM, Guenter Roeck wrote: > > > >>> bit 0 is the enable bit, and bit 1 enables interrupts. At address 0x08 (eg > >>> LPASS_QDSP6SS_WDOG_UNMASKED_INT_EN), bit 0 enables interrupts and bit 1 is > >>> undefined. > >> > >> I honestly don’t see anything at 0x8 for either blocks that looks like this. For the new block bit 0 is enabling and bit 1 enabled interrupts. > >> > > That is from the APQ8064 datasheet. > > So taken from the timer offset 0x0208A000 I just have a generic counter register CPU0_APCS_GPT0_CNT at 0x8 > > What doc are you looking at? > "Qualcomm Snapdragon 600 Processor APQ8064 Hardware Register Description" It is available for download from the Qualcomm web site. See chapter 12.10.3, "Watchdog timer registers". The register block is at 0x28882000. Registers are almost the same, except for the offset and the definition of the bits in the enable register. LPASS is "Low Power Audio Subsystem". Maybe it has its own watchdog. Guenter