Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751458AbcC2Ip5 (ORCPT ); Tue, 29 Mar 2016 04:45:57 -0400 Received: from mail.skyhub.de ([78.46.96.112]:36488 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750794AbcC2Ipz (ORCPT ); Tue, 29 Mar 2016 04:45:55 -0400 Date: Tue, 29 Mar 2016 10:45:49 +0200 From: Borislav Petkov To: tthayer@opensource.altera.com Cc: dougthompson@xmission.com, m.chehab@samsung.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, dinguyen@opensource.altera.com, grant.likely@linaro.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tthayer.linux@gmail.com Subject: Re: [PATCHv3 9/9] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry Message-ID: <20160329084549.GC3705@pd.tnic> References: <1458576106-24505-1-git-send-email-tthayer@opensource.altera.com> <1458576106-24505-10-git-send-email-tthayer@opensource.altera.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1458576106-24505-10-git-send-email-tthayer@opensource.altera.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1514 Lines: 50 On Mon, Mar 21, 2016 at 11:01:46AM -0500, tthayer@opensource.altera.com wrote: > From: Thor Thayer > > Add the device tree entries needed to support the Altera L2 > cache EDAC on the Arria10 chip. > > Signed-off-by: Thor Thayer > --- > v2 Match register value (l2-ecc@ffd06010) > v3 Set ecc_manager to beginning of system_manager. Add sysman > phandle. Move IRQs into ecc_manager from children. > --- > arch/arm/boot/dts/socfpga_arria10.dtsi | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi > index cce9e50..345ea97 100644 > --- a/arch/arm/boot/dts/socfpga_arria10.dtsi > +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi > @@ -599,6 +599,21 @@ > reg = <0xffe00000 0x40000>; > }; > > + eccmgr: eccmgr@ffd06000 { > + compatible = "altr,socfpga-a10-ecc-manager"; > + altr,sysmgr-syscon = <&sysmgr>; > + #address-cells = <1>; > + #size-cells = <1>; > + interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 IRQ_TYPE_LEVEL_HIGH>; > + ranges; > + > + l2-ecc@ffd06010 { > + compatible = "altr,socfpga-a10-l2-ecc"; > + reg = <0xffd06010 0x4>; > + }; > + }; > + > rst: rstmgr@ffd05000 { > #reset-cells = <1>; > compatible = "altr,rst-mgr"; > -- I've picked up all except this one: need an ACK for it too. Dinh, DT-people? -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply.