Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757275AbcC2QXM (ORCPT ); Tue, 29 Mar 2016 12:23:12 -0400 Received: from li153-180.members.linode.com ([109.74.206.180]:43594 "EHLO mail.tekno-soft.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751724AbcC2QXK (ORCPT ); Tue, 29 Mar 2016 12:23:10 -0400 X-Greylist: delayed 534 seconds by postgrey-1.27 at vger.kernel.org; Tue, 29 Mar 2016 12:23:10 EDT Subject: Re: [PATCH] i.MX6 PCIe: Fix imx6_pcie_deassert_core_reset() polarity To: Tim Harvey , Arnd Bergmann References: <23031613.R8qN30TbTq@wuerfel> <5741237.2X2Q0sCFQj@wuerfel> Cc: Lucas Stach , "linux-arm-kernel@lists.infradead.org" , "linux-pci@vger.kernel.org" , Richard Zhu , linux-kernel , =?UTF-8?Q?Krzysztof_Ha=c5=82asa?= , Bjorn Helgaas , =?UTF-8?Q?Petr_=c5=a0tetiar?= , Fabio Estevam From: Roberto Fichera Organization: TeknoSOFT Message-ID: <56FAA9C1.5060107@tekno-soft.it> Date: Tue, 29 Mar 2016 18:13:53 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-Intuitive-System-MailScanner-Information: Please contact the ISP for more information X-Intuitive-System-MailScanner-ID: 5E9A717727.A8E3F X-Intuitive-System-MailScanner: Found to be clean X-Intuitive-System-MailScanner-From: kernel@tekno-soft.it Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1598 Lines: 30 On 03/29/2016 05:10 PM, Tim Harvey wrote: > Arnd, > > Right, on the IMX the MSI interrupt is GIC-120 which is also the > legacy INTD and I do see that if I happen to put a radio in a slot > where due to swizzling its pin1 becomes INTD (GIC-120) the interrupt > does fire and the device works. Any other slot using GIC-123 (INTA), > GIC-122 (INTB), or GIC-121 (INTC) never fires so its very possible > that something in the designware core is masking out the legacy irqs. > I would also think this was something IMX specific, but I really don't > see any codepaths in pci-imx6.c that would cause that: a driver > requesting a legacy PCI would get a GIC interrupt which is handled by > the IMX6 gpc interrupt controller. > > Any dra7xxx, exynos, spear13xx, keystone, layerscape, hisi, qcom SoC > users of designware PCIe core out there that can verify PCI MSI and > legacy are both working at the same time? > > Lucas is the expert here and I believe he has the documentation for > the designware core that Freescale doens't provide with the IMX6 > documentation so hopefully he can provide some insight. He's the one > that has authored all the MSI support and has been using it. > > I typically advise our users to 'not' enable MSI because > architecturally you can spread 4 distinct legacy irq's across CPU's > better than a single shared irq. Don't know if I'm facing similar problem, however devices connected in miniPCI slot behind a PCIe-to-PCI bridge (MSI is disabled) using INTA all is working ok, including shared IRQ. In case of INTB will not work, and the GIC irq quite often get stuck.