Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754295AbcC3Sot (ORCPT ); Wed, 30 Mar 2016 14:44:49 -0400 Received: from smtprelay.synopsys.com ([198.182.47.9]:34086 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752517AbcC3Sor (ORCPT ); Wed, 30 Mar 2016 14:44:47 -0400 Subject: Re: [PATCH 1/2] usb: dwc3: core: Introduce dwc3_device_reinit() To: Felipe Balbi , John Youn , "Roger Quadros" References: <1458133551-3071-1-git-send-email-rogerq@ti.com> <1458133551-3071-2-git-send-email-rogerq@ti.com> <87r3fah8h3.fsf@intel.com> <87lh5ih6hs.fsf@intel.com> <56EC5452.8030509@synopsys.com> <56F03FD7.30202@synopsys.com> <874mbzyq1l.fsf@intel.com> <56F3376E.8050305@synopsys.com> <87d1qkxtbb.fsf@intel.com> From: John Youn CC: "nsekhar@ti.com" , "linux-usb@vger.kernel.org" , "linux-kernel@vger.kernel.org" Message-ID: <56FC1E92.60403@synopsys.com> Date: Wed, 30 Mar 2016 11:44:34 -0700 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <87d1qkxtbb.fsf@intel.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.9.139.66] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2774 Lines: 77 On 3/23/2016 11:52 PM, Felipe Balbi wrote: > > Hi, > > John Youn writes: >> [ text/plain ] >> On 3/21/2016 11:40 PM, Felipe Balbi wrote: >>> >>> Hi, >>> >>> John Youn writes: >>>> [ text/plain ] >>>> On 3/18/2016 12:17 PM, John Youn wrote: >>>>> On 3/16/2016 6:56 AM, Felipe Balbi wrote: >>>>>> >>>>>> heh, +john >>>>>> >>>>>> Felipe Balbi writes: >>>>>>> [ text/plain ] >>>>>>> >>>>>>> Hi, >>>>>>> >>>>>>> Roger Quadros writes: >>>>>>>> [ text/plain ] >>>>>>>> We will need this function for a workaround. >>>>>>>> The function issues a softreset only to the device >>>>>>>> controller and performs minimal re-initialization >>>>>>>> so that the device controller can be usable. >>>>>>>> >>>>>>>> As some code is similar to dwc3_core_init() take out >>>>>>>> common code into dwc3_get_gctl_quirks(). >>>>>>>> >>>>>>>> We add a new member (prtcap_mode) to struct dwc3 to >>>>>>>> keep track of the current mode in the PRTCAPDIR register. >>>>>>>> >>>>>>>> Signed-off-by: Roger Quadros >>>>>>> >>>>>>> I must say, I don't like this at all :-p There's ONE known silicon which >>>>>>> needs this because of a poor silicon integration which took an IP with a >>>>>>> known erratum where it can't be made to work on lower speeds and STILL >>>>>>> was integrated without a superspeed PHY. >>>>>>> >>>>>>> There's a reason why I never tried to push this upstream myself ;-) >>>>>>> >>>>>>> I'm really thinking we might be better off adding a quirk flag to skip >>>>>>> the metastability workaround and allow this ONE silicon to set the >>>>>>> controller to lower speed. >>>>>>> >>>>>>> John, can you check with your colleagues if we would ever fall into >>>>>>> STAR#9000525659 if we set maximum speed to high speed during driver >>>>>>> probe and never touch it again ? I would assume we don't really fall >>>>>>> into the metastability workaround, right ? We're not doing any sort of >>>>>>> PM for dwc3... >>>>>>> >>>> >>>> Hi Felipe, >>>> >>>> Do you mean to keep DCFG.speed to SS and set dwc->maximum_speed to HS? >>>> I don't see an issue with that as long as we always ignore >>>> dwc->maximum_speed when programming DCFG.speed for all affected >>>> versions of the core. As long as the DCFG.speed = SS, you should not >>>> hit the STAR. >>> >>> I actually mean changing DCFG.speed during driver probe and never >>> touching it again. Would that still cause problems ? >>> >> >> In that case I'm not sure. The engineer who would know is off until >> next week so I'll get back to you as soon as I can talk to him about >> it. > So the engineers said that this issue can occur while set to HS and the run/stop bit is changed so it seems that won't work. Regards, John