Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755442AbcCaIVf (ORCPT ); Thu, 31 Mar 2016 04:21:35 -0400 Received: from szxga01-in.huawei.com ([58.251.152.64]:63946 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754884AbcCaIV1 (ORCPT ); Thu, 31 Mar 2016 04:21:27 -0400 From: Jiancheng Xue To: , , , , , , , , CC: , , , , , , , , , , , , Jiancheng Xue Subject: [RESEND PATCH v10 0/6] ARM: hisi: Add initial support including clock driver for Hi3519 soc. Date: Thu, 31 Mar 2016 16:10:05 +0800 Message-ID: <1459411811-12390-1-git-send-email-xuejiancheng@hisilicon.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.212.71] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.56FCDE01.0128,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 24a93ded639db2e32e454fa3900e581c Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3248 Lines: 91 From: Jiancheng Xue Hello, Hi3519 soc is mainly used for ip camera and sport DV solutions. This patchset adds initial support for Hi3519 soc. It includes clock driver, arch configuration, debug uart configuration and device tree. It has been tested on hi3519 reference board. PATCH 3~6 in this serials have been acked. PATCH 1~2 are still waiting for being acked. Any comments will be appreciated! Thanks! Change Log ---------- v10: --Fixed issues pointed by Stephen Boyd. Use EXPORT_SYMBOL_GPL instead of EXPORT_SYMBOL. --Fixed some compile warning on some platforms v9: --Fixed issues pointed by Michael Turquette. Remove some unused header included by source files. Add a specific config option for compiling reset module. v8: --Made hi3519 clock driver can be compiled as a module --Fixed an issue in arch/arm/Kconfig.debug v7: --Rebased to v4.5-rc1 v6: -Changed clock driver to a real platform driver v5: -Adjusted clock and reset controller driver code v4: -Rebased to v4.4-rc7 -Divided patches according to Rob's comments -Added spi nodes in hi3519-demb.dts v3: -Rebased to v4.4-rc4 -Adjusted according to Arnd's comments -Removed ARCH_HI3519, using ARCH_HISI directly v2: -Rebased to v4.4-rc3 -Put dt-binding doc and header file in a separate patch. -Deleted unused clocks definitions. -Adjusted the ARCH_xxx order in Kconfig file -Renamed ARCH_HI3xxx to ARCH_36xx Jiancheng Xue (6): clk: hisilicon: export some hisilicon APIs to modules clk: hisilicon: add CRG driver for hi3519 soc ARM: hisi: add compatible string for Hi3519 soc ARM: debug: add hi3519 debug uart ARM: dt-bindings: add device tree bindings for Hi3519 sysctrl ARM: dts: add dts files for Hi3519 .../bindings/arm/hisilicon/hi3519-sysctrl.txt | 14 ++ .../devicetree/bindings/clock/hi3519-crg.txt | 46 +++++ arch/arm/Kconfig.debug | 10 ++ arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/hi3519-demb.dts | 42 +++++ arch/arm/boot/dts/hi3519.dtsi | 187 +++++++++++++++++++++ arch/arm/mach-hisi/hisilicon.c | 23 +-- drivers/clk/hisilicon/Kconfig | 15 ++ drivers/clk/hisilicon/Makefile | 2 + drivers/clk/hisilicon/clk-hi3519.c | 129 ++++++++++++++ drivers/clk/hisilicon/clk.c | 23 ++- drivers/clk/hisilicon/clk.h | 14 +- drivers/clk/hisilicon/reset.c | 124 ++++++++++++++ drivers/clk/hisilicon/reset.h | 32 ++++ include/dt-bindings/clock/hi3519-clock.h | 40 +++++ 15 files changed, 669 insertions(+), 34 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt create mode 100644 arch/arm/boot/dts/hi3519-demb.dts create mode 100644 arch/arm/boot/dts/hi3519.dtsi create mode 100644 drivers/clk/hisilicon/clk-hi3519.c create mode 100644 drivers/clk/hisilicon/reset.c create mode 100644 drivers/clk/hisilicon/reset.h create mode 100644 include/dt-bindings/clock/hi3519-clock.h -- 1.9.1