Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756037AbcCaI6Y (ORCPT ); Thu, 31 Mar 2016 04:58:24 -0400 Received: from mail-ob0-f174.google.com ([209.85.214.174]:35927 "EHLO mail-ob0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752419AbcCaI6V (ORCPT ); Thu, 31 Mar 2016 04:58:21 -0400 MIME-Version: 1.0 In-Reply-To: <20160325144834.GA27177@rob-hp-laptop> References: <1458838215-23314-1-git-send-email-narmstrong@baylibre.com> <1458838215-23314-13-git-send-email-narmstrong@baylibre.com> <20160325144834.GA27177@rob-hp-laptop> Date: Thu, 31 Mar 2016 10:58:20 +0200 Message-ID: Subject: Re: [PATCH v3 12/18] dt-bindings: Add PLX Technology OXNAS pinctrl and gpio bindings From: Linus Walleij To: Rob Herring Cc: Neil Armstrong , "linux-kernel@vger.kernel.org" , Russell King - ARM Linux , "linux-arm-kernel@lists.infradead.org" , "linux-gpio@vger.kernel.org" , "devicetree@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 751 Lines: 22 On Fri, Mar 25, 2016 at 3:48 PM, Rob Herring wrote: > On Thu, Mar 24, 2016 at 05:50:09PM +0100, Neil Armstrong wrote: >> Add pinctrl and gpio DT bindings for PLX Technology OXNAS SoC Family. >> This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins. >> >> Signed-off-by: Neil Armstrong >> + - plxtech,gpio-bank: Specifies which bank a controller owns. > > How is this used? That is used to give a unique ID number to the bank. Hardware often need this to cross-reference pin controllers to GPIO banks. I should add it as "gpio-bank" to the generic bindings instead, several platforms already use this and there is no point in having a vendor prefix in front of it. Yours, Linus Walleij