Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757166AbcCaOmQ (ORCPT ); Thu, 31 Mar 2016 10:42:16 -0400 Received: from mail.kernel.org ([198.145.29.136]:59330 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756233AbcCaOmP (ORCPT ); Thu, 31 Mar 2016 10:42:15 -0400 Date: Thu, 31 Mar 2016 09:42:09 -0500 From: Rob Herring To: Stefan Agner Cc: dri-devel@lists.freedesktop.org, shawnguo@kernel.org, kernel@pengutronix.de, airlied@linux.ie, daniel.vetter@ffwll.ch, jianwei.wang.chn@gmail.com, alison.wang@freescale.com, meng.yi@nxp.com, alexander.stein@systec-electronic.com, mturquette@baylibre.com, sboyd@codeaurora.org, mark.rutland@arm.com, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 4/8] drm/fsl-dcu: add extra clock for pixel clock Message-ID: <20160331144209.GA28867@rob-hp-laptop> References: <1459216802-32094-1-git-send-email-stefan@agner.ch> <1459216802-32094-5-git-send-email-stefan@agner.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1459216802-32094-5-git-send-email-stefan@agner.ch> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1728 Lines: 41 On Mon, Mar 28, 2016 at 06:59:58PM -0700, Stefan Agner wrote: > The Vybrid DCU variant has two independent clock inputs, one > for the registers (IPG bus clock) and one for the pixel clock. > Support this distinction in the DCU DRM driver while staying > backward compatible with devices providing only a single clock > (e.g. LS1021a SoC's). I'd suspect that both have 2 clocks, just the LS1021a either didn't model the IPG clock or connects both to the same source. The driver should support both, but all the dts's should be updated to have 2 clocks. > > Signed-off-by: Stefan Agner > --- > Documentation/devicetree/bindings/display/fsl,dcu.txt | 4 ++++ > drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 2 +- > drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 16 +++++++++++++++- > drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h | 1 + > 4 files changed, 21 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt b/Documentation/devicetree/bindings/display/fsl,dcu.txt > index ebf1be9..f299e1e 100644 > --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt > +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt > @@ -11,6 +11,10 @@ Required properties: > - big-endian Boolean property, LS1021A DCU registers are big-endian. > - fsl,panel: The phandle to panel node. > > +Optional properties: > +- clocks: Second handle for pixel clock. > +- clock-names: Second name "pix" for pixel clock. Document these in one place and just add a note that LS1021a only has 1 clock. > + > Examples: > dcu: dcu@2ce0000 { > compatible = "fsl,ls1021a-dcu"; > diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c