Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757665AbcCaTPq (ORCPT ); Thu, 31 Mar 2016 15:15:46 -0400 Received: from shards.monkeyblade.net ([149.20.54.216]:57581 "EHLO shards.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757230AbcCaTPo (ORCPT ); Thu, 31 Mar 2016 15:15:44 -0400 Date: Thu, 31 Mar 2016 15:15:42 -0400 (EDT) Message-Id: <20160331.151542.1145855002785328972.davem@davemloft.net> To: jszhang@marvell.com Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] net: mvpp2: replace MVPP2_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES From: David Miller In-Reply-To: <1459338821-343-1-git-send-email-jszhang@marvell.com> References: <1459338821-343-1-git-send-email-jszhang@marvell.com> X-Mailer: Mew version 6.6 on Emacs 24.5 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.5.12 (shards.monkeyblade.net [149.20.54.216]); Thu, 31 Mar 2016 12:15:43 -0700 (PDT) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 388 Lines: 12 From: Jisheng Zhang Date: Wed, 30 Mar 2016 19:53:41 +0800 > The mvpp2 ip maybe used in SoCs which may have have 64bytes cacheline > size. Replace the MVPP2_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES. > > And since dma_alloc_coherent() is always cacheline size aligned, so > remove the align checks. > > Signed-off-by: Jisheng Zhang Applied.