Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932077AbcCaUBu (ORCPT ); Thu, 31 Mar 2016 16:01:50 -0400 Received: from skprod2.natinst.com ([130.164.80.23]:38726 "EHLO ni.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1756307AbcCaUBt (ORCPT ); Thu, 31 Mar 2016 16:01:49 -0400 Date: Thu, 31 Mar 2016 15:01:47 -0500 From: Josh Cartwright To: punnaiah choudary kalluri Cc: linux-mm@kvack.org, "linux-kernel@vger.kernel.org" Subject: Re: Issue with ioremap Message-ID: <20160331200147.GA20530@jcartwri.amer.corp.natinst.com> References: MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) X-MIMETrack: Itemize by SMTP Server on US-AUS-MGWOut1/AUS/H/NIC(Release 8.5.3FP6 HF1218|December 12, 2014) at 03/31/2016 03:01:48 PM, Serialize by Router on US-AUS-MGWOut1/AUS/H/NIC(Release 8.5.3FP6 HF1218|December 12, 2014) at 03/31/2016 03:01:48 PM, Serialize complete at 03/31/2016 03:01:48 PM Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-03-31_08:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1548 Lines: 32 On Fri, Apr 01, 2016 at 01:13:06AM +0530, punnaiah choudary kalluri wrote: > Hi, > > We are using the pl353 smc controller for interfacing the nand in our zynq SOC. > The driver for this controller is currently under mainline review. > Recently we are moved to 4.4 kernel and observing issues with the driver. > while debug, found that the issue is with the virtual address returned from > the ioremap is not aligned to the physical address and causing nand > access failures. > the nand controller physical address starts at 0xE1000000 and the size is 16MB. > the ioremap function in 4.3 kernel returns the virtual address that is > aligned to the size > but not the case in 4.4 kernel. :(. I had actually ran into this, too, as I was evaluating the use of the upstream-targetted pl353 stuff; sorry I didn't say anything. > this controller uses the bits [31:24] as base address and use rest all > bits for configuring adders cycles, chip select information. so it > expects the virtual address also aligned to 0xFF000000 otherwise the > nand commands issued will fail. The driver _currently_ expects the virtual address to be 16M aligned, but is that a hard requirement? It seems possible that the driver could be written without this assumption, correct? This would mean that the driver would need to maintain the cs/cycles configuration state outside of the mapped virtual address, and then calculate + add the calculated offset to the base. Would that work? I had been meaning to give it a try, but haven't gotten around to it. Josh