Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933462AbcCaUhp (ORCPT ); Thu, 31 Mar 2016 16:37:45 -0400 Received: from down.free-electrons.com ([37.187.137.238]:56466 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1758552AbcCaUhn (ORCPT ); Thu, 31 Mar 2016 16:37:43 -0400 Date: Thu, 31 Mar 2016 22:37:35 +0200 From: Thomas Petazzoni To: David Miller Cc: jszhang@marvell.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES Message-ID: <20160331223735.32904e42@free-electrons.com> In-Reply-To: <20160331.151547.1889188465826831929.davem@davemloft.net> References: <1459338921-391-1-git-send-email-jszhang@marvell.com> <20160331.151547.1889188465826831929.davem@davemloft.net> Organization: Free Electrons X-Mailer: Claws Mail 3.12.0 (GTK+ 2.24.28; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 828 Lines: 29 Hello, On Thu, 31 Mar 2016 15:15:47 -0400 (EDT), David Miller wrote: > From: Jisheng Zhang > Date: Wed, 30 Mar 2016 19:55:21 +0800 > > > The mvneta is also used in some Marvell berlin family SoCs which may > > have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE > > usage with L1_CACHE_BYTES. > > > > And since dma_alloc_coherent() is always cacheline size aligned, so > > remove the align checks. > > > > Signed-off-by: Jisheng Zhang > > Applied. A new version of the patch was sent, which more rightfully uses cache_line_size(), see: "[PATCH v2] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with cache_line_size" Best regards, Thomas -- Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com