Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758711AbcDADb5 (ORCPT ); Thu, 31 Mar 2016 23:31:57 -0400 Received: from mail-bl2on0081.outbound.protection.outlook.com ([65.55.169.81]:14871 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753477AbcDADbx (ORCPT ); Thu, 31 Mar 2016 23:31:53 -0400 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=none action=none header.from=nxp.com; From: Yangbo Lu To: , , , , , , , , CC: Rob Herring , , Russell King , Jochen Friedrich , Joerg Roedel , Claudiu Manoil , , Bhupesh Sharma , "Zhao Qiang" , Kumar Gala , "Santosh Shilimkar" , , , Yangbo Lu Subject: [v7, 2/5] soc: fsl: add GUTS driver for QorIQ platforms Date: Fri, 1 Apr 2016 11:07:28 +0800 Message-ID: <1459480051-3701-3-git-send-email-yangbo.lu@nxp.com> X-Mailer: git-send-email 2.1.0.27.g96db324 In-Reply-To: <1459480051-3701-1-git-send-email-yangbo.lu@nxp.com> References: <1459480051-3701-1-git-send-email-yangbo.lu@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131039542221584704;(91ab9b29-cfa4-454e-5278-08d120cd25b8);() X-Forefront-Antispam-Report: CIP:192.88.168.50;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(1109001)(1110001)(339900001)(199003)(189002)(50466002)(19580395003)(1096002)(33646002)(92566002)(1220700001)(5003940100001)(19580405001)(551934003)(50226001)(50986999)(104016004)(189998001)(76176999)(11100500001)(5008740100001)(586003)(48376002)(5001770100001)(2906002)(36756003)(4326007)(575784001)(47776003)(105606002)(106466001)(87936001)(77096005)(229853001)(2950100001)(81166005)(86362001)(2201001)(7059030)(2101003)(473944003);DIR:OUT;SFP:1101;SCL:1;SRVR:DM2PR0301MB0717;H:tx30smr01.am.freescale.net;FPR:;SPF:Fail;MLV:sfv;A:1;MX:1;LANG:en; X-Microsoft-Exchange-Diagnostics: 1;BL2FFO11FD042;1:8VxUVHVH/HmuNoUdAWsYMUoweqYbX8YE5YZTTGf43ycE91+LJRejgAqaX42rf+ztHyPxc6Xg4J9PPZ3s4/yiDRAXjFV91eU2KuGikZWs0iBuIl3SeNQcU4ibpbfS6P1Nq/tGzfBwr4ub/dZ28RDzxHY607ZEP5GoV+6/7cGyf7OZ8TG7wYu2X9fJbFmcOgX8LqvnZ35HXzz8gfyW6TXVimORkM+d8Axe6oBFdfM7cY8TRvBPyys3f0XX++7itHz+k2WzZXqF2uqVcrAE/3IlXyerFndhvQQO2cg85CzZ8aktCrLX+ChkfpjXXIWWLmhmgMWAJclRZ/mh9Lxc8NhSrfukvXdKTQjkgBmr/Btl7t7oPUNAoe7oFqkeyZF27UZ3zdnYcVCZyMprc9eugYJNgECWkWvt6H9sVRMltQsVhGUlGl9rg/0VQrsd7IhD2WAfh3fItmUkvGu1JxX9uqqRX6v3JxdEHlA7pf+dqGe15oKR8aCde6aq9EJkF+52clxqAECaq2FMI3SwUt34HurEnMWYoBYZittHvdCtPeenLm3hK3mr48kTSeL5I5q0NCsOoBnPwiWnbcr4hKhRjTWpxsTSLweeAS0R4uxJF4QDXkRiPYroTd0VhcW2VAFwz5E2YGVe+IUJhKD0Cvc7b1hdJDVhB0hXmoCfTZyi5UlT3ryWZUKQOcX2C8VvqiI/31azZZ32kaYBy3FgRTeQOdgqig== MIME-Version: 1.0 Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: da8388ce-eb9a-444a-57df-08d359dc181a X-Microsoft-Exchange-Diagnostics: 1;DM2PR0301MB0717;2:uaHKq5qDjnwLoKlHZtDItgKrN0nf8hlsi09/Uk0ddeEx1qVjFN9odRWNEju84DtQQuVvwJVll+5sYWLy97ldH8iNw/xeURSaSk+mz0/be3tikcHcm1ITV6P5BS9nVynLK9uBpCM4sJ+ZFgNpS75sWiI4k+/uEnQYDhrG5nn5Axy8TFPAl2DTJSEYml6UslBh;3:YH9RF+UcplALM7vFVrv9KGtxzNj75UZFA96YN+6bPx9IzV912xazzp9bP5OuGHHxVCipGX+6j5NNr6hOLbmSy70X9R6EtRZvBK1VfhCvOm40gvEMIEq6yGirKtP7f1X5X7mgXna/ONYMynKtnCfDpDpZN2C+IS40/Id/mQNXoheM9J1My7yNi0rDp9C5Sg+Zwq/TAxgi3OubUf3pQmSRhEf3z29+PAYKpIil8qIxQL0= X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:DM2PR0301MB0717; X-Microsoft-Exchange-Diagnostics: 1;DM2PR0301MB0717;25:rVtRVc3YpI+Y2aRcLw/rToUW8cIUeUkPlIQP/KddLQUYiWXq9QMmsvpAR0RsRGD4bX65cqfQCq06O7uACmSZ9NXQxJ6Re2WK9Nd51SXZ8Ke9PT9h6X68041KlDS9JE3qWf+cIfLnvK2uJk7ndVsHG9VYyPpLoaERjuKrmHEmFC/5gK6w4VRDQsVnfGGsHdxZKHoAMOWGJA8TnH/GluYUl0OiX9lOajP+zIP8485ibgLn7Y08/B1V4zCy46Es4GT+cbR4ttc39MEvFCtbwLRqfDgsvEx2JSS9aldpdyBspzEZoDM61tv0G4ZUeImwOR/+PipAZ4m/BKi0afQX1fCSbUxHhi/5pIAA8AKhUkD6xq9E0VLKuwTM4cayAN9SvMzDe2O0HsRIL5ApH04pin4zYRINUfL6fv1/OBdW76oDrwOzD7hSwlvAO+yLTJ+6+zipOi6fjmmV4z9SSGpzucc14W+KTaVt3kj+64vGSnq5LxhHF3u7mq8WiC7TX8LiwWBIxdl+r4iW/9nkfKJlTcKUOIkh+BxEn85tIlrBhuR3CJYTJk13hcFezEjyLJpgoG7On8qPbyVUYEqW520vuqKEboF2vb6TUWdziFE7WRji7BU= X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(2401047)(13017025)(13018025)(13024025)(13023025)(8121501046)(5005006)(13015025)(3002001)(10201501046);SRVR:DM2PR0301MB0717;BCL:0;PCL:0;RULEID:(400006);SRVR:DM2PR0301MB0717; X-Microsoft-Exchange-Diagnostics: 1;DM2PR0301MB0717;4:DnXx1DFtkBcA2DI5oMzXYNhYPZila/XLSn1ymP+x5rkP8c3KI7zY8Qk6o9m4iRLxa0hhC0xyTDzLcGfimkS+BVo1VPpyUzigg7kSFNZMa9PoAZ8hTEac3yBVbehUnxiTTtNeHQipk1Iw1vNn2Vvng3YXpzA+BjG0Vg9YcbwFbKXI8cYxuvK4AFHBAtUECElg4nfEUm/sddfJfGcqoeThx3XzHFCmloWnl/6DUSMZLLVIXB485MXhB9tZf+j9CElSniiXyrAM57KA4GCdYdsQARuhvrqWLSEmLIDPV2GAghf4crygOsqxr6HVq4RUcQMsVXJUHZCiv16BRreq8urEcPmhgfSczgUPbwKzjj89Ts7rUsX9eIlZLAYst/eisC8Xzg0ZqYXRfoiOnvcHAL2DMlbshxJRm6okCtQgMX8SwjSbWktJroLKrWwLvlrQGfsHlFuenkOfOhIOmNG3ZQVShg== X-Forefront-PRVS: 0899B47777 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1;DM2PR0301MB0717;23:pXwfhVju5EzxO+VQhJip7acpugcwlAR5lr/IbGr?= =?us-ascii?Q?2nc0zDSXzxAkZk1KY8B3pX5+woxWsbHlwWqlVEEtcl6x/GHGyHPlu+LREbxh?= =?us-ascii?Q?d7AGeOiIIypVZwDNMi3paLbABUmFFlqUukgMYzNU04Pa6bLw3N7hd4y3Pkh2?= =?us-ascii?Q?hLmgf8JeFhK3sjXjHjR8kLp6Qd/MZjrgM+y2Po8OwZ/NgscchGfYtNY5X8fa?= =?us-ascii?Q?gHnx5DUf1u7/Ip5/xRwaPa7Dve3aE7lKvyJpmaFT3fhDUlwiBsEKNQeefeQB?= =?us-ascii?Q?ZXW4MGSb0EZ5I80psHK7chuWZNPaRCBKaXoDUIoJHQmLafypEXrhdwicZ1ju?= =?us-ascii?Q?+Tj/A4oinAq17VfBNDeZgKONzH1EVsVG9J4DKwiI/wh6tMrrG+BwNbN34WKb?= =?us-ascii?Q?jwpyhsKn90jYfeJr9GkrKU9CsHxsiGeolyelaDGMfLMC4Yq605axQRvy/KF1?= =?us-ascii?Q?FpsfrQUUvcgK7GJhlX6Ye1hzP8dfJwNZwaaYYTO2dBpkKPl4RA/4/7WfFTQP?= =?us-ascii?Q?VHHMsJOUlul62JhEgXz+7DSUp5CF+A0XedeSr8amLAFn8ZIT4AG51xPNRR3O?= =?us-ascii?Q?+kNYu9zWvcI0XoZQI3PLzUxa5Qv4tO2jrKyFIj1PS4zmcmLQHVFo74JyWrJL?= =?us-ascii?Q?wgLGZDnuClZSEG1RsYEZAvczYfC1XGCZSYXAbDsbMvyzOw+WjHxtjRaL195l?= =?us-ascii?Q?+QrPjF7/9li45H4bm7MNAm80woiHful8opQJBr13mh7uenCncc2LxxtI2xrR?= =?us-ascii?Q?xwi+dv0Wl2cSc4JtO0tGaHfoiCPQ7R3g6mSWXP1UWX0BIG8solUiC0HEDOQm?= =?us-ascii?Q?qD83NXl3xZxkGBf9AnYpX4LDUpWXGDlCXZzpWKdkDfKJDyipDQFepgE4yG/3?= =?us-ascii?Q?9umbwmln5Qz+OPR+GH/M8nlXnisI93Sya6HIXuOu5re1sc2f/bbEfqkzB0Ku?= =?us-ascii?Q?WFu5kDEV0LqxjCv+ra/sZmHgWQxwmY7I8gb72cXn/or/OtG6QuNKgT6m+smM?= =?us-ascii?Q?JUWPty9HnbqHufzTF4E3lLTtDaeQxAizqG6cgncaBWJV67+dQyCoY6OBlR4c?= =?us-ascii?Q?5moQZD6KaXMgmR6CDilkz3LW8mxXyEMCF2YKZnD50+o73BiuSKCb5Ko5K8P4?= =?us-ascii?Q?EzzYReSNrrTs=3D?= X-Microsoft-Exchange-Diagnostics: 1;DM2PR0301MB0717;5:b3JmvojkogGZFw+XGIuaNznjM6V1TcZa3MIQIDXU2KmnAInjaDqza9gi+Re0OMKSHGAh3W5qQ4j6yXAVWiJHQI4ROqiJpvkHntlQfwrBpehaGj538/T6bJrgeMy7y/J/LQgmYDhb72Q6KA1O9VT5pTpt2gr1kaYgQ7VTlvOzCrI=;24:PmPT6eaIwzyMIRVjdl3r5EzeRK2KaGXGNVtwtYZrSDT550TcDZS9w79FxPIbM8lLeSawIGxnoc1SyJwc3fKk8RvZrNgR35o5WaKqxAVHWj0= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Apr 2016 03:17:01.8464 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;Ip=[192.88.168.50];Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR0301MB0717 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 12790 Lines: 342 The global utilities block controls power management, I/O device enabling, power-onreset(POR) configuration monitoring, alternate function selection for multiplexed signals,and clock control. This patch adds GUTS driver to manage and access global utilities block. Signed-off-by: Yangbo Lu --- Changes for v2: - None Changes for v3: - None Changes for v4: - Added this patch Changes for v5: - Modified copyright info - Changed MODULE_LICENSE to GPL - Changed EXPORT_SYMBOL_GPL to EXPORT_SYMBOL - Made FSL_GUTS user-invisible - Added a complete compatible list for GUTS - Stored guts info in file-scope variable - Added mfspr() getting SVR - Redefined GUTS APIs - Called fsl_guts_init rather than using platform driver - Removed useless parentheses - Removed useless 'extern' key words Changes for v6: - Made guts thread safe in fsl_guts_init Changes for v7: - Removed 'ifdef' for function declaration in guts.h --- drivers/soc/Kconfig | 2 +- drivers/soc/fsl/Kconfig | 8 ++++ drivers/soc/fsl/Makefile | 1 + drivers/soc/fsl/guts.c | 119 +++++++++++++++++++++++++++++++++++++++++++++++ include/linux/fsl/guts.h | 98 +++++++++++++++++++------------------- 5 files changed, 179 insertions(+), 49 deletions(-) create mode 100644 drivers/soc/fsl/Kconfig create mode 100644 drivers/soc/fsl/guts.c diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index cb58ef0..7106463 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -2,7 +2,7 @@ menu "SOC (System On Chip) specific Drivers" source "drivers/soc/bcm/Kconfig" source "drivers/soc/brcmstb/Kconfig" -source "drivers/soc/fsl/qe/Kconfig" +source "drivers/soc/fsl/Kconfig" source "drivers/soc/mediatek/Kconfig" source "drivers/soc/qcom/Kconfig" source "drivers/soc/rockchip/Kconfig" diff --git a/drivers/soc/fsl/Kconfig b/drivers/soc/fsl/Kconfig new file mode 100644 index 0000000..b313759 --- /dev/null +++ b/drivers/soc/fsl/Kconfig @@ -0,0 +1,8 @@ +# +# Freescale SOC drivers +# + +source "drivers/soc/fsl/qe/Kconfig" + +config FSL_GUTS + bool diff --git a/drivers/soc/fsl/Makefile b/drivers/soc/fsl/Makefile index 203307f..02afb7f 100644 --- a/drivers/soc/fsl/Makefile +++ b/drivers/soc/fsl/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_QUICC_ENGINE) += qe/ obj-$(CONFIG_CPM) += qe/ +obj-$(CONFIG_FSL_GUTS) += guts.o diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c new file mode 100644 index 0000000..fa155e6 --- /dev/null +++ b/drivers/soc/fsl/guts.c @@ -0,0 +1,119 @@ +/* + * Freescale QorIQ Platforms GUTS Driver + * + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +struct guts { + struct ccsr_guts __iomem *regs; + bool little_endian; +}; + +static struct guts *guts; +static DEFINE_MUTEX(guts_lock); + +u32 fsl_guts_get_svr(void) +{ + u32 svr = 0; + + if (!guts || !guts->regs) { +#ifdef CONFIG_PPC + svr = mfspr(SPRN_SVR); +#endif + return svr; + } + + if (guts->little_endian) + svr = ioread32(&guts->regs->svr); + else + svr = ioread32be(&guts->regs->svr); + + return svr; +} +EXPORT_SYMBOL(fsl_guts_get_svr); + +/* + * Table for matching compatible strings, for device tree + * guts node, for Freescale QorIQ SOCs. + */ +static const struct of_device_id guts_of_match[] = { + /* For T4 & B4 Series SOCs */ + { .compatible = "fsl,qoriq-device-config-1.0", }, + /* For P Series SOCs */ + { .compatible = "fsl,qoriq-device-config-2.0", }, + { .compatible = "fsl,p1010-guts", }, + { .compatible = "fsl,p1020-guts", }, + { .compatible = "fsl,p1021-guts", }, + { .compatible = "fsl,p1022-guts", }, + { .compatible = "fsl,p1023-guts", }, + { .compatible = "fsl,p2020-guts", }, + /* For BSC Series SOCs */ + { .compatible = "fsl,bsc9131-guts", }, + { .compatible = "fsl,bsc9132-guts", }, + /* For MPC85xx Series SOCs */ + { .compatible = "fsl,mpc8536-guts", }, + { .compatible = "fsl,mpc8544-guts", }, + { .compatible = "fsl,mpc8548-guts", }, + { .compatible = "fsl,mpc8568-guts", }, + { .compatible = "fsl,mpc8569-guts", }, + { .compatible = "fsl,mpc8572-guts", }, + /* For Layerscape Series SOCs */ + { .compatible = "fsl,ls1021a-dcfg", }, + { .compatible = "fsl,ls1043a-dcfg", }, + { .compatible = "fsl,ls2080a-dcfg", }, + {} +}; + +int fsl_guts_init(void) +{ + struct device_node *np; + int ret; + + mutex_lock(&guts_lock); + /* Initialize guts only once */ + if (guts) { + ret = guts->regs ? 0 : -ENOMEM; + goto out; + } + + np = of_find_matching_node(NULL, guts_of_match); + if (!np) { + ret = -ENODEV; + goto out; + } + + guts = kzalloc(sizeof(*guts), GFP_KERNEL); + if (!guts) { + ret = -ENOMEM; + goto out; + } + + guts->little_endian = of_property_read_bool(np, "little-endian"); + + guts->regs = of_iomap(np, 0); + if (!guts->regs) { + ret = -ENOMEM; + kfree(guts); + goto out; + } + + of_node_put(np); + ret = 0; +out: + mutex_unlock(&guts_lock); + return ret; +} +EXPORT_SYMBOL(fsl_guts_init); diff --git a/include/linux/fsl/guts.h b/include/linux/fsl/guts.h index 649e917..ac3103b 100644 --- a/include/linux/fsl/guts.h +++ b/include/linux/fsl/guts.h @@ -29,83 +29,85 @@ * #ifdefs. */ struct ccsr_guts { - __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ - __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ - __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ - __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */ - __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ - __be32 pordevsr2; /* 0x.0014 - POR device status register 2 */ + u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ + u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ + u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ + u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */ + u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ + u32 pordevsr2; /* 0x.0014 - POR device status register 2 */ u8 res018[0x20 - 0x18]; - __be32 porcir; /* 0x.0020 - POR Configuration Information Register */ + u32 porcir; /* 0x.0020 - POR Configuration Information Register */ u8 res024[0x30 - 0x24]; - __be32 gpiocr; /* 0x.0030 - GPIO Control Register */ + u32 gpiocr; /* 0x.0030 - GPIO Control Register */ u8 res034[0x40 - 0x34]; - __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */ + u32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */ u8 res044[0x50 - 0x44]; - __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */ + u32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */ u8 res054[0x60 - 0x54]; - __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ - __be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */ - __be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */ + u32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ + u32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */ + u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */ u8 res06c[0x70 - 0x6c]; - __be32 devdisr; /* 0x.0070 - Device Disable Control */ + u32 devdisr; /* 0x.0070 - Device Disable Control */ #define CCSR_GUTS_DEVDISR_TB1 0x00001000 #define CCSR_GUTS_DEVDISR_TB0 0x00004000 - __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */ + u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */ u8 res078[0x7c - 0x78]; - __be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */ - __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ - __be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */ - __be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */ - __be32 pmcdr; /* 0x.008c - 4Power management clock disable register */ - __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */ - __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */ - __be32 ectrstcr; /* 0x.0098 - Exception reset control register */ - __be32 autorstsr; /* 0x.009c - Automatic reset status register */ - __be32 pvr; /* 0x.00a0 - Processor Version Register */ - __be32 svr; /* 0x.00a4 - System Version Register */ + u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */ + u32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ + u32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */ + u32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */ + u32 pmcdr; /* 0x.008c - 4Power management clock disable register */ + u32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */ + u32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */ + u32 ectrstcr; /* 0x.0098 - Exception reset control register */ + u32 autorstsr; /* 0x.009c - Automatic reset status register */ + u32 pvr; /* 0x.00a0 - Processor Version Register */ + u32 svr; /* 0x.00a4 - System Version Register */ u8 res0a8[0xb0 - 0xa8]; - __be32 rstcr; /* 0x.00b0 - Reset Control Register */ + u32 rstcr; /* 0x.00b0 - Reset Control Register */ u8 res0b4[0xc0 - 0xb4]; - __be32 iovselsr; /* 0x.00c0 - I/O voltage select status register + u32 iovselsr; /* 0x.00c0 - I/O voltage select status register Called 'elbcvselcr' on 86xx SOCs */ u8 res0c4[0x100 - 0xc4]; - __be32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers + u32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers There are 16 registers */ u8 res140[0x224 - 0x140]; - __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */ - __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */ + u32 iodelay1; /* 0x.0224 - IO delay control register 1 */ + u32 iodelay2; /* 0x.0228 - IO delay control register 2 */ u8 res22c[0x604 - 0x22c]; - __be32 pamubypenr; /* 0x.604 - PAMU bypass enable register */ + u32 pamubypenr; /* 0x.604 - PAMU bypass enable register */ u8 res608[0x800 - 0x608]; - __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */ + u32 clkdvdr; /* 0x.0800 - Clock Divide Register */ u8 res804[0x900 - 0x804]; - __be32 ircr; /* 0x.0900 - Infrared Control Register */ + u32 ircr; /* 0x.0900 - Infrared Control Register */ u8 res904[0x908 - 0x904]; - __be32 dmacr; /* 0x.0908 - DMA Control Register */ + u32 dmacr; /* 0x.0908 - DMA Control Register */ u8 res90c[0x914 - 0x90c]; - __be32 elbccr; /* 0x.0914 - eLBC Control Register */ + u32 elbccr; /* 0x.0914 - eLBC Control Register */ u8 res918[0xb20 - 0x918]; - __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */ - __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */ - __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */ + u32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */ + u32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */ + u32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */ u8 resb2c[0xe00 - 0xb2c]; - __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */ + u32 clkocr; /* 0x.0e00 - Clock Out Select Register */ u8 rese04[0xe10 - 0xe04]; - __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ + u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ u8 rese14[0xe20 - 0xe14]; - __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ - __be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */ + u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ + u32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */ u8 rese28[0xf04 - 0xe28]; - __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */ - __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */ + u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */ + u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */ u8 resf0c[0xf2c - 0xf0c]; - __be32 itcr; /* 0x.0f2c - Internal transaction control register */ + u32 itcr; /* 0x.0f2c - Internal transaction control register */ u8 resf30[0xf40 - 0xf30]; - __be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */ - __be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */ + u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */ + u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */ } __attribute__ ((packed)); +u32 fsl_guts_get_svr(void); +int fsl_guts_init(void); /* Alternate function signal multiplex control */ #define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x)) -- 2.1.0.27.g96db324