Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752421AbcDASm3 (ORCPT ); Fri, 1 Apr 2016 14:42:29 -0400 Received: from gloria.sntech.de ([95.129.55.99]:58828 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751284AbcDASm1 convert rfc822-to-8bit (ORCPT ); Fri, 1 Apr 2016 14:42:27 -0400 From: Heiko Stuebner To: Jaehoon Chung Cc: Guodong Xu , shawn.lin@rock-chips.com, "robh+dt@kernel.org" , pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, ulf.hansson@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xinwei Kong , Zhangfei Gao , "linux-mmc@vger.kernel.org" Subject: Re: [PATCH v3 2/2] mmc: dw_mmc: add resets support to dw_mmc Date: Fri, 01 Apr 2016 20:42 +0200 Message-ID: <1754831.FONmYVUinF@phil> User-Agent: KMail/4.14.10 (Linux/4.3.0-1-amd64; KDE/4.14.14; x86_64; ; ) In-Reply-To: <56FBBB2F.5030308@samsung.com> References: <1459322696-29919-1-git-send-email-guodong.xu@linaro.org> <1459322696-29919-3-git-send-email-guodong.xu@linaro.org> <56FBBB2F.5030308@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="iso-8859-1" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1127 Lines: 29 Am Mittwoch, 30. M?rz 2016, 20:40:31 schrieb Jaehoon Chung: > modified Rob's mail address. > > On 03/30/2016 04:24 PM, Guodong Xu wrote: > > mmc registers may in abnormal state if mmc is used in bootloader, > > eg. to support booting from eMMC. So we need reset mmc registers > > when kernel boots up, instead of assuming mmc is in clean state. > > Do you mean mmc(card side) register or dwmmc host controller's register on > host side? > > According to dwmmc controller TMR, there are two reset signals. One is > reset_n, other is rst_n. It seems this patch is relevant to reset_n(For > host). (rst_n is hardware reset for card.) > > So could you clarify better? Then it's helpful to me for understanding.. I think that actually means a reset of controller IP block logic, outside the control of the dw_mmc block itself. On Rockchip SoCs this gets triggered from the CRU (clock and reset unit), so I guess if I'm reading the manual correctly, should be the reset_n signal of the ip block. rst_n on the other hand gets triggered through a dw_mmc register setting and is already handled by the dw_mmc driver. Heiko