Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759439AbcDBBOm (ORCPT ); Fri, 1 Apr 2016 21:14:42 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:36015 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756111AbcDBBOj (ORCPT ); Fri, 1 Apr 2016 21:14:39 -0400 Date: Fri, 1 Apr 2016 18:14:36 -0700 From: Stephen Boyd To: Rob Herring Cc: yassinjaffer@gmail.com, dev@linux-sunxi.org, Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Maxime Ripard , Chen-Yu Tsai , Emilio =?iso-8859-1?Q?L=F3pez?= , Michael Turquette , Hans de Goede , Reinder de Haan , Jens Kuske , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/Allwinner sunXi SoC support" , open list , "open list:COMMON CLK FRAMEWORK" Subject: Re: [PATCH] clk: sunxi: Add CSI (camera's Sensors Interface) module clock driver for sun[457]i Message-ID: <20160402011436.GA18567@codeaurora.org> References: <1458204222-31149-1-git-send-email-yassinjaffer@gmail.com> <1458204222-31149-2-git-send-email-yassinjaffer@gmail.com> <20160319235905.GA16539@rob-hp-laptop> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20160319235905.GA16539@rob-hp-laptop> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 676 Lines: 21 On 03/19, Rob Herring wrote: > On Thu, Mar 17, 2016 at 07:43:42PM +1100, yassinjaffer@gmail.com wrote: > > From: Yassin Jaffer > > > > This patch adds a composite clock type consisting of > > a clock gate, mux, configurable dividers, and a reset control. > > > > Signed-off-by: Yassin Jaffer > > --- > > Documentation/devicetree/bindings/clock/sunxi.txt | 1 + > > I wish someone would just add all the sunxi clocks in one pass instead > of one by one. > > Acked-by: Rob Herring Me too! -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project