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Message-id: <5701E55B.1080503@samsung.com>
Date: Mon, 04 Apr 2016 12:54:03 +0900
From: Jaehoon Chung <jh80.chung@samsung.com>
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To: Heiko Stuebner <heiko@sntech.de>
Cc: Guodong Xu <guodong.xu@linaro.org>, shawn.lin@rock-chips.com,
        "robh+dt@kernel.org" <robh+dt@kernel.org>, pawel.moll@arm.com,
        mark.rutland@arm.com, ijc+devicetree@hellion.org.uk,
        galak@codeaurora.org, ulf.hansson@linaro.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        Xinwei Kong <kong.kongxinwei@hisilicon.com>,
        Zhangfei Gao <zhangfei.gao@linaro.org>,
        "linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>
Subject: Re: [PATCH v3 2/2] mmc: dw_mmc: add resets support to dw_mmc
References: <1459322696-29919-1-git-send-email-guodong.xu@linaro.org>
 <1459322696-29919-3-git-send-email-guodong.xu@linaro.org>
 <56FBBB2F.5030308@samsung.com> <1754831.FONmYVUinF@phil>
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On 04/02/2016 03:42 AM, Heiko Stuebner wrote:
> Am Mittwoch, 30. M?rz 2016, 20:40:31 schrieb Jaehoon Chung:
>> modified Rob's mail address.
>>
>> On 03/30/2016 04:24 PM, Guodong Xu wrote:
>>> mmc registers may in abnormal state if mmc is used in bootloader,
>>> eg. to support booting from eMMC. So we need reset mmc registers
>>> when kernel boots up, instead of assuming mmc is in clean state.
>>
>> Do you mean mmc(card side) register or dwmmc host controller's register on
>> host side?
>>
>> According to dwmmc controller TMR, there are two reset signals. One is
>> reset_n, other is rst_n. It seems this patch is relevant to reset_n(For
>> host). (rst_n is hardware reset for card.)
>>
>> So could you clarify better? Then it's helpful to me for understanding..
> 
> I think that actually means a reset of controller IP block logic, outside 
> the control of the dw_mmc block itself.
> 
> On Rockchip SoCs this gets triggered from the CRU (clock and reset unit), so 
> I guess if I'm reading the manual correctly, should be the reset_n signal of 
> the ip block.
> 
> rst_n on the other hand gets triggered through a dw_mmc register setting and 
> is already handled by the dw_mmc driver.

Right, this patch is for reset_n signal. I didn't have seen the SoC that reset_n is designed.
(Or i didn't realize...)
If Rockchip is used from CRU (clock and reset unit), then i think that it makes sense.

Thanks for explanation. 

Best Regards,
Jaehoon Chung

> 
> 
> Heiko
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