Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754591AbcDGCmC (ORCPT ); Wed, 6 Apr 2016 22:42:02 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:31294 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751430AbcDGCmA (ORCPT ); Wed, 6 Apr 2016 22:42:00 -0400 Date: Thu, 7 Apr 2016 10:37:34 +0800 From: Jisheng Zhang To: Gabriele Paoloni , "jingoohan1@gmail.com" , "pratyush.anand@gmail.com" , "bhelgaas@google.com" CC: "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v2] PCI: designware: move remaining rc setup code to dw_pcie_setup_rc() Message-ID: <20160407103734.55e72da7@xhacker> In-Reply-To: References: <1458128433-3020-1-git-send-email-jszhang@marvell.com> X-Mailer: Claws Mail 3.13.2 (GTK+ 2.24.30; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-04-07_02:,, signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1601100000 definitions=main-1604070038 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1805 Lines: 51 Hi Gabriele, On Wed, 6 Apr 2016 14:50:29 +0000 Gabriele Paoloni wrote: > Hi, sorry to be late on this > > > -----Original Message----- > > From: linux-kernel-owner@vger.kernel.org [mailto:linux-kernel- > > owner@vger.kernel.org] On Behalf Of Jisheng Zhang > > Sent: 16 March 2016 11:41 > > To: jingoohan1@gmail.com; pratyush.anand@gmail.com; bhelgaas@google.com > > Cc: linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm- > > kernel@lists.infradead.org; Jisheng Zhang > > Subject: [PATCH v2] PCI: designware: move remaining rc setup code to > > dw_pcie_setup_rc() > > > > dw_pcie_setup_rc(), as its name indicates, setups the RC. But current > > dw_pcie_host_init() also contains some necessary rc setup code. > > > > Another reason: the host may lost power during suspend to ram, the RC > > need to be re-setup after resume. The rc can't be correctly resumed > > without the rc setup code in dw_pcie_host_init(). > > > > So this patch moves the code to dw_pcie_setup_rc() to address the above > > two issues. After this patch, each pcie designware driver users could > > call dw_pcie_setup_rc() to re-setup rc when resume back. > > I think this patch breaks the Hisilicon driver... > > Our driver performs linkup setup in UEFI therefore we do not call > dw_pcie_setup_rc(), we only call dw_pcie_host_init(). Thanks for the information. So pcie-hisi rely on UEFI to do something similar in dw_pcie_setup_rc(), this comes to a common driver implement question: should linux device driver rely on bootloader to configure HW device? Is it acceptable that pcie-hisi adds a call to dw_pcie_setup_rc() in hisi_add_pcie_port()? Thanks, Jisheng > > Maybe better to group the part of code to be moved in as separate > function... > > Thanks and sorry for late reply. > > Gab > >