Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755010AbcDIC3J (ORCPT ); Fri, 8 Apr 2016 22:29:09 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:55527 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754665AbcDIC3I (ORCPT ); Fri, 8 Apr 2016 22:29:08 -0400 Subject: Re: [PATCH v5 6/9] irqchip/gic-v3: Parse and export virtual GIC information To: Julien Grall , kvmarm@lists.cs.columbia.edu References: <1459769860-6629-1-git-send-email-julien.grall@arm.com> <1459769860-6629-7-git-send-email-julien.grall@arm.com> Cc: al.stone@linaro.org, kvm@vger.kernel.org, marc.zyngier@arm.com, linux-kernel@vger.kernel.org, fu.wei@linaro.org, Thomas Gleixner , Jason Cooper , linux-arm-kernel@lists.infradead.org, gg@slimlogic.co.uk From: Shanker Donthineni Message-ID: <570868EE.9090200@codeaurora.org> Date: Fri, 8 Apr 2016 21:29:02 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <1459769860-6629-7-git-send-email-julien.grall@arm.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 6958 Lines: 241 Hi Julien, On 04/04/2016 06:37 AM, Julien Grall wrote: > Fill up the recently introduced gic_kvm_info with the hardware > information used for virtualization. > > Signed-off-by: Julien Grall > Cc: Thomas Gleixner > Cc: Jason Cooper > Cc: Marc Zyngier > > --- > Changes in v5: > - Remove the alignment check for GICV. It's already done in the > KVM code. > - Fix initialization of KVM with ACPI. > > Changes in v4: > - Change the flow to call gic_kvm_set_info only when all the > mandatory information are valid. > - Remove unecessary code in ACPI parsing (the virtual control > interface doesn't exist for GICv3). > - Rework commit message > - Rework the ACPI support as it didn't collect hardware info for > virtualization when there is more than 1 redistributor region > > Changes in v3: > - Add ACPI support > > Changes in v2: > - Use 0 rather than a negative value to know when the maintenance > IRQ > is not present. > - Use resource for vcpu and vctrl > --- > drivers/irqchip/irq-gic-v3.c | 110 > ++++++++++++++++++++++++++++++++- > include/linux/irqchip/arm-gic-common.h | 1 + > 2 files changed, 110 insertions(+), 1 deletion(-) > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index 50e87e6..08afbfe 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -28,6 +28,7 @@ > #include > > #include > +#include > #include > > #include > @@ -56,6 +57,8 @@ struct gic_chip_data { > static struct gic_chip_data gic_data __read_mostly; > static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; > > +static struct gic_kvm_info gic_v3_kvm_info; > + > #define gic_data_rdist() > (this_cpu_ptr(gic_data.rdists.rdist)) > #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) > #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + > SZ_64K) > @@ -901,6 +904,30 @@ static int __init gic_validate_dist_version(void > __iomem *dist_base) > return 0; > } > > +static void __init gic_of_setup_kvm_info(struct device_node *node) > +{ > + int ret; > + struct resource r; > + u32 gicv_idx; > + > + gic_v3_kvm_info.type = GIC_V3; > + > + gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); > + if (!gic_v3_kvm_info.maint_irq) > + return; > + > + if (of_property_read_u32(node, "#redistributor-regions", > + &gicv_idx)) > + gicv_idx = 1; > + > + gicv_idx += 3; /* Also skip GICD, GICC, GICH */ > + ret = of_address_to_resource(node, gicv_idx, &r); > + if (!ret) > + gic_v3_kvm_info.vcpu = r; > + > + gic_set_kvm_info(&gic_v3_kvm_info); > +} > + > static int __init gic_of_init(struct device_node *node, struct > device_node *parent) > { > void __iomem *dist_base; > @@ -952,8 +979,10 @@ static int __init gic_of_init(struct device_node > *node, struct device_node *pare > > err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, > redist_stride, &node->fwnode); > - if (!err) > + if (!err) { > + gic_of_setup_kvm_info(node); > return 0; > + } > > out_unmap_rdist: > for (i = 0; i < nr_redist_regions; i++) > @@ -974,6 +1003,9 @@ static struct > struct redist_region *redist_regs; > u32 nr_redist_regions; > bool single_redist; > + u32 maint_irq; > + int maint_irq_mode; > + phys_addr_t vcpu_base; > } acpi_data __initdata; > > static void __init > @@ -1110,7 +1142,81 @@ static bool __init acpi_validate_gic_table(struct > acpi_subtable_header *header, > return true; > } > > +static int __init gic_acpi_parse_virt_madt_gicc(struct > acpi_subtable_header *header, > + const unsigned long end) > +{ > + struct acpi_madt_generic_interrupt *gicc = > + (struct acpi_madt_generic_interrupt *)header; > + int maint_irq_mode; > + static int first_madt = true; > + > + maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? > + ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; > + Do you think GICC parameters are valid for an unusable processor? If not we need a validation check here, some thing like this to skip GICC subtable entry. if (!(gicc->flags & ACPI_MADT_ENABLED)) return 0; > + if (first_madt) { > + first_madt = false; > + > + acpi_data.maint_irq = gicc->vgic_interrupt; > + acpi_data.maint_irq_mode = maint_irq_mode; > + acpi_data.vcpu_base = gicc->gicv_base_address; > + > + return 0; > + } > + > + /* > + * The maintenance interrupt and GICV should be the same for every > CPU > + */ > + if ((acpi_data.maint_irq != gicc->vgic_interrupt) || > + (acpi_data.maint_irq_mode != maint_irq_mode) || > + (acpi_data.vcpu_base != gicc->gicv_base_address)) > + return -EINVAL; > + > + return 0; > +} > + > +static bool __init gic_acpi_collect_virt_info(void) > +{ > + int count; > + > + count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, > + gic_acpi_parse_virt_madt_gicc, 0); > + > + return (count > 0); > +} > + > #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) > +#define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) > +#define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) > + > +static void __init gic_acpi_setup_kvm_info(void) > +{ > + int irq; > + > + if (!gic_acpi_collect_virt_info()) { > + pr_warn("Unable to get hardware information used for > virtualization\n"); > + return; > + } > + > + gic_v3_kvm_info.type = GIC_V3; > + > + irq = acpi_register_gsi(NULL, acpi_data.maint_irq, > + acpi_data.maint_irq_mode, > + ACPI_ACTIVE_HIGH); > + if (irq <= 0) > + return; > + > + gic_v3_kvm_info.maint_irq = irq; > + > + if (acpi_data.vcpu_base) { > + struct resource *vcpu = &gic_v3_kvm_info.vcpu; > + > + vcpu->flags = IORESOURCE_MEM; > + vcpu->start = acpi_data.vcpu_base; > + vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; > + } > + > + gic_set_kvm_info(&gic_v3_kvm_info); > +} > > static int __init > gic_acpi_init(struct acpi_subtable_header *header, const unsigned long > end) > @@ -1159,6 +1265,8 @@ gic_acpi_init(struct acpi_subtable_header *header, > const unsigned long end) > goto out_fwhandle_free; > > acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); > + gic_acpi_setup_kvm_info(); > + > return 0; > > out_fwhandle_free: > diff --git a/include/linux/irqchip/arm-gic-common.h > b/include/linux/irqchip/arm-gic-common.h > index ef34f6f..c647b05 100644 > --- a/include/linux/irqchip/arm-gic-common.h > +++ b/include/linux/irqchip/arm-gic-common.h > @@ -15,6 +15,7 @@ > > enum gic_type { > GIC_V2, > + GIC_V3, > }; > > struct gic_kvm_info { -- Shanker Donthineni Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project