Date: Sat, 9 Apr 2016 12:03:33 +0100
From: Marc Zyngier <marc.zyngier@arm.com>
To: Jon Hunter <jonathanh@nvidia.com>
Cc: Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>,
        =?ISO-8859-1?Q?Beno=EEt?= Cousson <bcousson@baylibre.com>,
        Tony Lindgren <tony@atomide.com>, Rob Herring <robh+dt@kernel.org>,
        Pawel Moll <pawel.moll@arm.com>, Mark Rutland <mark.rutland@arm.com>,
        Ian Campbell <ijc+devicetree@hellion.org.uk>,
        "Kumar Gala" <galak@codeaurora.org>,
        Stephen Warren <swarren@wwwdotorg.org>,
        "Thierry Reding" <thierry.reding@gmail.com>,
        Kevin Hilman <khilman@kernel.org>,
        Geert Uytterhoeven <geert@linux-m68k.org>,
        Grygorii Strashko <grygorii.strashko@ti.com>,
        Lars-Peter Clausen <lars@metafoo.de>,
        Linus Walleij <linus.walleij@linaro.org>,
        <linux-tegra@vger.kernel.org>, <linux-omap@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 05/15] irqchip: Mask the non-type/sense bits when
 translating an IRQ
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	<1458224359-32665-6-git-send-email-jonathanh@nvidia.com>
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On Thu, 17 Mar 2016 14:19:09 +0000
Jon Hunter <jonathanh@nvidia.com> wrote:

> The firmware parameter that contains the IRQ sense bits may also contain
> other data. When return the IRQ type, bits outside of these sense bits
> should be masked. If these bits are not masked and
> irq_create_fwspec_mapping() is called to map an IRQ, then the comparison
> of the type returned from irq_domain_translate() will never match
> that returned by irq_get_trigger_type() (because this function masks the
> none sense bits) and so we will always call irq_set_irq_type() to program
> the type even if it was not really necessary.
> 
> Currently, the downside to this is unnecessarily re-programmming the type
> but nevertheless this should be avoided.
> 
> The Tegra LIC, TI Crossbar and GIC-V3 irqchips all have client instances
> (from reviewing the device-tree sources) where bits outside the IRQ sense
> bits are set, but do not mask these bits. Therefore, ensure these bits
> are masked for these irqchips.

For GICv3, this shouldn't be the case. The DT clearly says that the 3rd
field should only contain the trigger description. It looks like people
have been copying their GICv2 DT and simply slapped the v3 description
in the middle, without changing their interrupt specifiers. Duh.

I guess this patch doesn't hurt though.

> 
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>

Acked-by: Marc Zyngier <marc.zyngier@arm.com>

	M.
-- 
Jazz is not dead. It just smells funny.