Date: Tue, 12 Apr 2016 23:57:45 +0200
From: Wolfram Sang <wsa@the-dreams.de>
To: Shardar Shariff Md <smohammed@nvidia.com>
Cc: ldewangan@nvidia.com, swarren@wwwdotorg.org, thierry.reding@gmail.com,
        linux-i2c@vger.kernel.org, linux-tegra@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] i2c: tegra: enable multi master mode
Message-ID: <20160412215745.GJ1526@katana>
References: <1457961738-1927-1-git-send-email-smohammed@nvidia.com>
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On Mon, Mar 14, 2016 at 06:52:18PM +0530, Shardar Shariff Md wrote:
> Enable multi-master mode in I2C_CNFG reg based on hw features.
> Using single/multi-master mode bit introduced for Tegra210,
> whereas multi-master mode is enabled by default in HW for T124 and
> earlier Tegra SOC. Enabling this bit doesn't explicitly start
> treating the bus has having multiple masters, but will start
> checking for arbitration lost and reporting when it occurs.
>=20
> The Tegra210 I2C controller supports single/multi master mode.
> Add chipdata for Tegra210 and its compatibility string so that
> Tegra210 will select data that enables multi master mode correctly.
>=20
> Do below prerequisites for multi-master bus if "multi-master"
> dt property entry is added.
>  1. Enable 1st level clock always set.
>  2. Disable 2nd level clock gating (slcg which
>     is supported from T124 SOC and later chips)
>=20
> Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>

Applied to for-next, thanks!


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