Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031136AbcDMMCx (ORCPT ); Wed, 13 Apr 2016 08:02:53 -0400 Received: from mga11.intel.com ([192.55.52.93]:12731 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1031049AbcDMMCu (ORCPT ); Wed, 13 Apr 2016 08:02:50 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,479,1455004800"; d="scan'208";a="954032437" Message-ID: <1460549027.6620.131.camel@linux.intel.com> Subject: Re: [PATCH v1 12/12] serial: 8250_lpss: enable DMA on Intel Quark UART From: Andy Shevchenko To: "Bryan O'Donoghue" , Andy Shevchenko Cc: Vinod Koul , "linux-kernel@vger.kernel.org" , dmaengine , Greg Kroah-Hartman , "Puustinen, Ismo" , Heikki Krogerus , "linux-serial@vger.kernel.org" Date: Wed, 13 Apr 2016 15:03:47 +0300 In-Reply-To: <1460546565.19152.148.camel@nexus-software.ie> References: <1460061433-63750-1-git-send-email-andriy.shevchenko@linux.intel.com> <1460061433-63750-13-git-send-email-andriy.shevchenko@linux.intel.com> <1460388795.19152.38.camel@nexus-software.ie> <1460478320.19152.92.camel@nexus-software.ie> <1460479824.6620.121.camel@linux.intel.com> <1460546565.19152.148.camel@nexus-software.ie> Organization: Intel Finland Oy Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.18.5.1-1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1116 Lines: 35 On Wed, 2016-04-13 at 12:22 +0100, Bryan O'Donoghue wrote: > On Tue, 2016-04-12 at 19:50 +0300, Andy Shevchenko wrote: > > > > > > > > I haven't read your V2 yet but on this, I'd suggest raising the > > burst > > > > > > size to 32 bytes for UART (no higher) we found during bringup that > > > larger sizes "fall-over and die" but, anything up to 32 bytes is > > > OK > > - > > > > > > and therefore you should be able to reduce the number of > > > bursts/interrupts etc. > > It can't be more that FIFO size and recommendation as far as I know > > is > > FIFO/2, which is exactly 8 bytes. > Why not ? Because a probability of FIFO overrun. There is a big chapter ("Peripheral Burst Transaction Requests") in dw_apb_dmac_db.pdf covering this. > > We went as high as 32 bytes previously in the BSP with no obvious > errors. > > At 8 bytes or 1/2 of the FIFO size I'd ask the question is DMA even > worth it i.e. does it take more time to setup and execute a DMA > transaction @ 1/2 FIFO size than just writing straight into the FIFO ? -- Andy Shevchenko Intel Finland Oy