Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933734AbcDMNYs (ORCPT ); Wed, 13 Apr 2016 09:24:48 -0400 Received: from exsmtp01.microchip.com ([198.175.253.37]:41962 "EHLO email.microchip.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932737AbcDMNYr (ORCPT ); Wed, 13 Apr 2016 09:24:47 -0400 From: Purna Chandra Mandal To: , CC: Mark Brown , Purna Chandra Mandal , Kumar Gala , Ian Campbell , Rob Herring , Pawel Moll , Mark Rutland , Subject: [PATCH v2 1/2] spi: pic32-sqi: add binding document for PIC32 Quad-SPI driver. Date: Wed, 13 Apr 2016 18:52:57 +0530 Message-ID: <1460553778-1662-1-git-send-email-purna.mandal@microchip.com> X-Mailer: git-send-email 1.8.3.1 MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1575 Lines: 45 Document Device tree bindings for the quad SPI peripheral found on Microchip PIC32 class devices. Signed-off-by: Purna Chandra Mandal Cc: Kumar Gala Cc: Ian Campbell Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Mark Brown --- Changes in v2: None Documentation/devicetree/bindings/spi/sqi-pic32.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/sqi-pic32.txt diff --git a/Documentation/devicetree/bindings/spi/sqi-pic32.txt b/Documentation/devicetree/bindings/spi/sqi-pic32.txt new file mode 100644 index 0000000..5af9fab --- /dev/null +++ b/Documentation/devicetree/bindings/spi/sqi-pic32.txt @@ -0,0 +1,18 @@ +Microchip PIC32 Quad SPI controller +----------------------------------- +Required properties: +- compatible: Should be "microchip,pic32mzda-sqi". +- reg: Address and length of SQI controller register space. +- interrupts: Should contain SQI interrupt. +- clocks: Should contain phandle of two clocks in sequence, clock that drives + clock on SPI bus and clock that drives SQI controller. +- clock-names: Should be "spi_ck" and "reg_ck" in order. + +Example: + sqi1: sqi@1f8e2000 { + compatible = "microchip,pic32mzda-sqi"; + reg = <0x1f8e2000 0x200>; + clocks = <&rootclk REF2CLK>, <&rootclk PB5CLK>; + clock-names = "spi_ck", "reg_ck"; + interrupts = <169 IRQ_TYPE_LEVEL_HIGH>; + }; -- 1.8.3.1