Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965197AbcDMOe7 (ORCPT ); Wed, 13 Apr 2016 10:34:59 -0400 Received: from mail-wm0-f43.google.com ([74.125.82.43]:38099 "EHLO mail-wm0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933981AbcDMOe5 (ORCPT ); Wed, 13 Apr 2016 10:34:57 -0400 Message-ID: <1460558093.19152.151.camel@nexus-software.ie> Subject: Re: [PATCH v1 12/12] serial: 8250_lpss: enable DMA on Intel Quark UART From: "Bryan O'Donoghue" To: Andy Shevchenko , Andy Shevchenko Cc: Vinod Koul , "linux-kernel@vger.kernel.org" , dmaengine , Greg Kroah-Hartman , "Puustinen, Ismo" , Heikki Krogerus , "linux-serial@vger.kernel.org" Date: Wed, 13 Apr 2016 15:34:53 +0100 In-Reply-To: <1460549027.6620.131.camel@linux.intel.com> References: <1460061433-63750-1-git-send-email-andriy.shevchenko@linux.intel.com> <1460061433-63750-13-git-send-email-andriy.shevchenko@linux.intel.com> <1460388795.19152.38.camel@nexus-software.ie> <1460478320.19152.92.camel@nexus-software.ie> <1460479824.6620.121.camel@linux.intel.com> <1460546565.19152.148.camel@nexus-software.ie> <1460549027.6620.131.camel@linux.intel.com> Organization: Nexus Software Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.16.5-1ubuntu3.1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 362 Lines: 9 On Wed, 2016-04-13 at 15:03 +0300, Andy Shevchenko wrote: > Because a probability of FIFO overrun. > > There is a big chapter ("Peripheral Burst Transaction Requests") in > dw_apb_dmac_db.pdf covering this. I thought there was flow control between the controller and the FIFO here ? I don't have the spec SoC spec for the UART to hand but, if memory serves...