Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753165AbcDMRX3 (ORCPT ); Wed, 13 Apr 2016 13:23:29 -0400 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:39190 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753076AbcDMRX1 (ORCPT ); Wed, 13 Apr 2016 13:23:27 -0400 Date: Wed, 13 Apr 2016 18:23:18 +0100 From: Mark Brown To: Giuseppe CAVALLARO Cc: Peter Griffin , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, lgirdwood@gmail.com, srinivas.kandagatla@gmail.com, maxime.coquelin@st.com, patrice.chotard@st.com, lee.jones@linaro.org, devicetree@vger.kernel.org, Youssef TRIKI Message-ID: <20160413172318.GC29471@sirena.org.uk> References: <1460474204-5351-1-git-send-email-peter.griffin@linaro.org> <1460474204-5351-3-git-send-email-peter.griffin@linaro.org> <20160413061514.GI14664@sirena.org.uk> <570DFC44.8060408@st.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="69pVuxX8awAiJ7fD" Content-Disposition: inline In-Reply-To: <570DFC44.8060408@st.com> X-Cookie: Love thy neighbor, tune thy piano. User-Agent: Mutt/1.5.24 (2015-08-30) X-SA-Exim-Connect-IP: 2a01:348:6:8808:fab::3 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Re: [PATCH 2/5] regulator: st-flashss: Add a regulator driver for flashss vsense. X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1821 Lines: 44 --69pVuxX8awAiJ7fD Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Apr 13, 2016 at 09:59:00AM +0200, Giuseppe CAVALLARO wrote: > On 4/13/2016 8:15 AM, Mark Brown wrote: > >>>+static void st_get_satinize_powerup_voltage(struct st_vsense *vsense) > >>>+{ > >or am I missing something? Why do we need to do this anyway, it's very > >surprsing? > This functions is to sanitize the vsense voltages when the regulator > is probed and in some circumstances the reset value of this register > does not reflect the hw status/config. For example, by default, after > the reset, the bit 0 is set so the EMMC, inside the flash subsystem, > is supposed to operate at 3v3. But the latched bit 24 can be 0 on > a platform where it is actually set at 1v8. > So the bit 0 must be reset to keep this coherent and to allow MMC > framework to properly setup the Vdd when the framework starts. I'm afraid I can't follow that explanation, perhaps because I don't know anything about the content of this register except for these three bits. I think we do need a comment in the driver explaining what's going on, and probably a simplification of the code too if my understanding of the effect of all those operations is correct. --69pVuxX8awAiJ7fD Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBCAAGBQJXDoCEAAoJECTWi3JdVIfQEz8H/RPhtGRQrOquL5xePbKThd7c QvZyD98ASeRzcyX7DqlGVtyVwVErGLJZF9XRanv9z7CuxUqxoNcLbNLypEh+v1ly nwhAOITteBH7i2JjbxypVqLGpZMbKViAKKBR0/yXYdbMmqR2U6JunkCom4ooaiuh 5gij/xURWJkBpIwjMacJwJoDDhlZQU8wSa1HUa43Sj10V9+KA5N9njhTwE0yWZGo QdAzzDrdRpWVXzQE86VZuSAD0j3nQ8W1qjb5z5poU/qSW5EtJ1u4b/jbjztLepmj 3B+WqRvkkx4w+hI8ym3uuMNoyvhP+bMZxpKuwItMua9z7dHFTcr+IpyxSHd9+EM= =/N0I -----END PGP SIGNATURE----- --69pVuxX8awAiJ7fD--