Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751261AbcDNEBH (ORCPT ); Thu, 14 Apr 2016 00:01:07 -0400 Received: from mail-am1on0062.outbound.protection.outlook.com ([157.56.112.62]:8000 "EHLO emea01-am1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751072AbcDNEBF (ORCPT ); Thu, 14 Apr 2016 00:01:05 -0400 From: Yunhui Cui To: =?gb2312?B?QmVhbiBIdW8gu/Sx87HzIChiZWFuaHVvKQ==?= , "linux-mtd@lists.infradead.org" , "dwmw2@infradead.org" , "computersforpeace@gmail.com" , "han.xu@freescale.com" CC: Yunhui Cui , Yao Yuan , "linux-kernel@vger.kernel.org" , "linux-mtd@lists.infradead.org" , "linux-arm-kernel@lists.infradead.org" Subject: RE: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection Thread-Topic: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection Thread-Index: AdF1UHMSTv33b1QGWUOd5LMzc8yOJwLqWRwQAIjWOgAEuIAWgA== Date: Thu, 14 Apr 2016 03:45:33 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: micron.com; dkim=none (message not signed) header.d=none;micron.com; dmarc=none action=none header.from=nxp.com; x-originating-ip: [123.151.195.1] x-ms-office365-filtering-correlation-id: ed1617c6-ad2b-4d13-52a7-08d364173bcd x-microsoft-exchange-diagnostics: 1;AM2PR04MB0722;5:MnLPZ+poAy48Lot1B2HCVjUjGS6oOTBBnoOTqZSvn1/oCbHRi3bZOYfLL9I5G7mt99Lx2l1gluOxVYA9SIuga3uHZU7BZfeGkgzR0MGJQ5nZKv3Gwb7bm6y6J7G8sGO6YFVUcFLS9DecWeBw/u7Ntg==;24:XjDaT+Z+VPJ7kVCa0OMQP5KFGk0RacJ3YyOJ9vmaim0dIKE1U1MweeWEWbPyd/BoRJKecpX1r/U3zxLNuPl0pB3505qSs/8tVfta4CEIVB0= x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:AM2PR04MB0722; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(601004)(2401047)(5005006)(8121501046)(3002001)(10201501046)(6055026);SRVR:AM2PR04MB0722;BCL:0;PCL:0;RULEID:;SRVR:AM2PR04MB0722; x-forefront-prvs: 0912297777 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(53754006)(66654002)(377454003)(13464003)(9686002)(4326007)(54356999)(3846002)(3280700002)(1220700001)(1096002)(76176999)(3660700001)(586003)(6116002)(102836003)(2906002)(5008740100001)(2201001)(92566002)(189998001)(10400500002)(76576001)(575784001)(50986999)(2501003)(5001770100001)(86362001)(122556002)(2900100001)(5002640100001)(74316001)(19580405001)(19580395003)(77096005)(5003600100002)(81166005)(5004730100002)(33656002)(66066001)(87936001)(2950100001)(7059030);DIR:OUT;SFP:1101;SCL:1;SRVR:AM2PR04MB0722;H:DB5PR0401MB1912.eurprd04.prod.outlook.com;FPR:;SPF:None;MLV:sfv;LANG:en; spamdiagnosticoutput: 1:23 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="gb2312" MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Apr 2016 03:45:33.8146 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM2PR04MB0722 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id u3E41CuJ023881 Content-Length: 4498 Lines: 119 Hi all, I will send another patch set to replace this patch set. This patch set need not be reviewed more, Many thanks! Thanks Yunhui -----Original Message----- From: Bean Huo ?????? (beanhuo) [mailto:beanhuo@micron.com] Sent: Monday, March 21, 2016 10:56 AM To: Yunhui Cui; Yunhui Cui Cc: linux-mtd@lists.infradead.org; dwmw2@infradead.org; computersforpeace@gmail.com; han.xu@freescale.com; linux-kernel@vger.kernel.org; linux-mtd@lists.infradead.org; linux-arm-kernel@lists.infradead.org; Yao Yuan Subject: RE: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection Hi, Yunhai You mean that EVCR.bit7 cannot clear(enable quad mode) if not write SR.bit7 to 0? They don't have any connection each other. > -----Original Message----- > From: Yunhui Cui [mailto:yunhui.cui@nxp.com] > Sent: Friday, March 18, 2016 6:09 PM > To: Bean Huo ?????? (beanhuo); Yunhui Cui > Cc: linux-mtd@lists.infradead.org; dwmw2@infradead.org; > computersforpeace@gmail.com; han.xu@freescale.com; > linux-kernel@vger.kernel.org; linux-mtd@lists.infradead.org; > linux-arm-kernel@lists.infradead.org; Yao Yuan > Subject: RE: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW > protection > > Hi Bean, > > Thanks for your suggestions very much. > Yes, the flash N25Q128A status register write enable/disable bit is > disable in initial state. > But, This patch aims to clear status registerV bit[7](write > enable/disable bit) to 0, which enables the bit. > Frankly speaking, I also don't want to add this patch. > The reason for this is that clear status register bit[7] to 0 is a > must to set quad mode to Enhanced Volatile Configuration Register > using command SPINOR_OP_WD_EVCR. Otherwise it will output "Micron EVCR > Quad bit not clear" in spi-nor.c I looked up the datasheet, but I > really don't find out any connection between status register > bit[7](write enable/disable bit) equals 0 and seting quad mode to Enhanced Volatile Configuration Register. > > Just as I want to send the issue to Micron team , could you give me > some solutions ? > > > Thanks > Yunhui > > -----Original Message----- > From: Bean Huo ?????? (beanhuo) [mailto:beanhuo@micron.com] > Sent: Thursday, March 03, 2016 9:39 PM > To: Yunhui Cui > Cc: linux-mtd@lists.infradead.org; dwmw2@infradead.org; > computersforpeace@gmail.com; han.xu@freescale.com; > linux-kernel@vger.kernel.org; linux-mtd@lists.infradead.org; > linux-arm-kernel@lists.infradead.org; Yao Yuan; Yunhui Cui > Subject: Re: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW > protection > > > From: Yunhui Cui > > To: , , > > > > Cc: , , > > , , Yunhui > > Cui > > > > Subject: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW > > protection > > Message-ID: > <1456988044-37061-4-git-send-email-B56489@freescale.com> > > Content-Type: text/plain > > > > From: Yunhui Cui > > > > For Micron family ,The status register write enable/disable bit, > > provides hardware data protection for the device. > > When the enable/disable bit is set to 1, the status register > > nonvolatile bits become read-only and the WRITE STATUS REGISTER > > operation will not execute. > > > > Signed-off-by: Yunhui Cui > > --- > > drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++ > > 1 file changed, 9 insertions(+) > > > > diff --git a/drivers/mtd/spi-nor/spi-nor.c > > b/drivers/mtd/spi-nor/spi-nor.c index ed0c19c..917f814 100644 > > --- a/drivers/mtd/spi-nor/spi-nor.c > > +++ b/drivers/mtd/spi-nor/spi-nor.c > > @@ -39,6 +39,7 @@ > > > > #define SPI_NOR_MAX_ID_LEN 6 > > #define SPI_NOR_MAX_ADDR_WIDTH 4 > > +#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f > > > > struct flash_info { > > char *name; > > @@ -1238,6 +1239,14 @@ int spi_nor_scan(struct spi_nor *nor, const > > char *name, enum read_mode mode) > > write_sr(nor, 0); > > } > > > > + if (JEDEC_MFR(info) == SNOR_MFR_MICRON) { > > + ret = read_sr(nor); > > + ret &= SPI_NOR_MICRON_WRITE_ENABLE; > > + > For Micron the status register write enable/disable bit, its > default/factory value is disable. > Can here first check ,then program? > > + write_enable(nor); > > + write_sr(nor, ret); > > + } > > + > > if (!mtd->name) > > mtd->name = dev_name(dev); > > mtd->priv = nor;