Subject: Re: [PATCH V4 4/7] ARM64, ACPI, PCI: I/O Remapping Table (IORT)
 initial support.
To: Tomasz Nowicki <tn@semihalf.com>, Sinan Kaya <okaya@codeaurora.org>,
        tglx@linutronix.de, jason@lakedaemon.net, rjw@rjwysocki.net,
        lorenzo.pieralisi@arm.com, robert.richter@caviumnetworks.com,
        shijie.huang@arm.com, Suravee.Suthikulpanit@amd.com,
        hanjun.guo@linaro.org
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 <570E645A.9010600@arm.com> <570E6794.4080409@semihalf.com>
 <570E6B2C.3060700@arm.com> <570EB78E.4060705@codeaurora.org>
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Cc: al.stone@linaro.org, mw@semihalf.com, graeme.gregory@linaro.org,
        Catalin.Marinas@arm.com, will.deacon@arm.com,
        linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, ddaney.cavm@gmail.com
From: Marc Zyngier <marc.zyngier@arm.com>
Organization: ARM Ltd
Message-ID: <570F4886.70405@arm.com>
Date: Thu, 14 Apr 2016 08:36:38 +0100
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On 14/04/16 08:20, Tomasz Nowicki wrote:
> On 13.04.2016 23:18, Sinan Kaya wrote:
>> On 4/13/2016 11:52 AM, Marc Zyngier wrote:
>>>>> Sure. Please see:
>>>>> http://infocenter.arm.com/help/topic/com.arm.doc.den0049a/DEN0049A_IO_Remapping_Table.pdf
>>>>> 3.1.1.5 PCI root complex node
>>>>> PCI Segment number -> The PCI segment number, as in MCFG and as
>>>>> returned by _SEG in the namespace.
>>>>>
>>>>> So IORT spec states that pci_segment_number corresponds to the segment
>>>>> number from MCFG table and _SEG method. Here is my patch which makes
>>>>> sure pci_domain_nr(bus) is set properly:
>>>>> https://lkml.org/lkml/2016/2/16/418
>>> Lovely. So this series is actually dependent on the PCI one. I guess we
>>> need to solve that one first, because IORT seems pretty pointless if we
>>> don't have PCI support. What's the plan?
>>
>> Would it be OK to split the PCI specific section of the patch and continue
>> review? PCI is a user of the IORT table. Not the other way around.
> 
> I need to disagree. What would be the use case for patches w/o "PCI part" ?

Quite. PCI (as a subsystem) doesn't need IORT at all, thank you very
much. GIC (implementing MSI) and SMMU (implementing DMA) do, by virtue
of RID/SID/DID being translated all over the place.

So by the look of it, the dependency chain is GIC+SMMU->IORT->PCI.

The GIC changes here are pretty mechanical, and not that interesting.
The stuff that needs sorting quickly is PCI, because all this work is
pointless if we don't have it.

At the risk of sounding like a stuck record: What's the plan?

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...