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Date: Thu, 14 Apr 2016 16:25:30 +0100
From: Mark Brown <broonie@kernel.org>
To: Giuseppe CAVALLARO <peppe.cavallaro@st.com>
Cc: Peter Griffin <peter.griffin@linaro.org>,
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On Thu, Apr 14, 2016 at 04:15:34PM +0200, Giuseppe CAVALLARO wrote:
> On 4/13/2016 7:23 PM, Mark Brown wrote:

> 	/*
> 	 * After resetting, the CONFIG_REG_PSW_<xxx> are set, this
> 	 * means 3v3 operating voltage.
> 	 * The CONFIG_LATCHED_PSW_<xxx> must be used to fix the previous
> 	 * bits so operating at 1v8 if this is the real HW configuration
> 	 * at boot time.
> 	 */
> 	if (!(value & TOP_VSENSE_CONFIG_LATCHED_PSW_EMMC))
> 		value &= ~TOP_VSENSE_CONFIG_REG_PSW_EMMC;

That's definitely better.

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