Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752602AbcDOAGd (ORCPT ); Thu, 14 Apr 2016 20:06:33 -0400 Received: from mail-oi0-f51.google.com ([209.85.218.51]:32901 "EHLO mail-oi0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751867AbcDOAGb (ORCPT ); Thu, 14 Apr 2016 20:06:31 -0400 MIME-Version: 1.0 In-Reply-To: <1458576969-13309-3-git-send-email-andi@firstfloor.org> References: <1458576969-13309-1-git-send-email-andi@firstfloor.org> <1458576969-13309-3-git-send-email-andi@firstfloor.org> From: Andy Lutomirski Date: Thu, 14 Apr 2016 17:06:10 -0700 Message-ID: Subject: Re: [PATCH 2/9] x86: Add support for rd/wr fs/gs base To: Andi Kleen Cc: X86 ML , "linux-kernel@vger.kernel.org" , Andi Kleen Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 587 Lines: 16 On Mon, Mar 21, 2016 at 9:16 AM, Andi Kleen wrote: > From: Andi Kleen > > Introduction: > > IvyBridge added four new instructions to directly write the fs and gs > 64bit base registers. Previously this had to be done with a system > call to write to MSRs. The main use case is fast user space threading > and switching the fs/gs registers quickly there. Another use > case is having (relatively) cheap access to a new address > register per thread. I'm queuing up a variant of this patch. I'll send it out for review when it's ready. --Andy