Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752014AbcDOOXu (ORCPT ); Fri, 15 Apr 2016 10:23:50 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:2469 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751285AbcDOOXs (ORCPT ); Fri, 15 Apr 2016 10:23:48 -0400 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 15 Apr 2016 07:21:05 -0700 Message-ID: <5710F6CA.6060700@nvidia.com> Date: Fri, 15 Apr 2016 19:42:26 +0530 From: Laxman Dewangan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: Jon Hunter , , , , , , CC: , , , Subject: Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control References: <1460473007-11535-1-git-send-email-ldewangan@nvidia.com> <1460473007-11535-7-git-send-email-ldewangan@nvidia.com> <5710F7A4.5070902@nvidia.com> In-Reply-To: <5710F7A4.5070902@nvidia.com> X-Originating-IP: [10.19.65.30] X-ClientProxiedBy: DRHKMAIL103.nvidia.com (10.25.59.17) To bgmail102.nvidia.com (10.25.59.11) Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2532 Lines: 55 On Friday 15 April 2016 07:46 PM, Jon Hunter wrote: > On 12/04/16 15:56, Laxman Dewangan wrote: >> NVIDIA Tegra210 supports the IO pads which can operate at 1.8V >> or 3.3V I/O voltage levels. Also IO pads can be configured for >> power down state if it is not in used. SW needs to configure the >> voltage level of IO pads based on IO rail voltage and its power >> state based on platform usage. >> >> Add DT binding document for detailing the DT properties for >> configuring IO pads voltage levels and its power state. >> >> Signed-off-by: Laxman Dewangan > [snip] > >> +Required subnode-properties: >> +========================== >> +- pins : An array of strings. Each string contains the name of an IO pads. Valid >> + values for these names are listed below. >> + >> +Optional subnode-properties: >> +========================== >> +-nvidia,io-rail-voltage: Integer. The voltage level of IO pads. The >> + valid values are 1.8V and 3.3V. Macros are >> + defined for these voltage levels in >> + >> + Use TEGRA210_IO_RAIL_1800000UV for 1.8V >> + Use TEGRA210_IO_RAIL_3300000UV for 3.3V >> + >> +-nvidia,io-pad-deep-power-down: Integer, representing the deep power down state >> + of the IO pads. If this is enable then IO pads >> + will be in power down state and interface is not >> + enabled for any transaction. This is power >> + saving mode of the IO pads. The macros are >> + defined for enable/disable in >> + >> + TEGRA210_IO_PAD_DEEP_POWER_DOWN_DISABLE for >> + disable. >> + TEGRA210_IO_PAD_DEEP_POWER_DOWN_ENABLE for >> + enable. >> +Valid values for pin are: >> + audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, >> + dbg, debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, >> + gpio, hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, >> + pex-ctrl, sdmmc1, sdmmc3, spi, spi-hv, uart, usb-bias, usb0, >> + usb1, usb2, usb3. > Thinking about this some more, the above are not IO pads but supply > pads, AFAICT. And these supply pads, are supplying the voltage to > various IO pads. I am not sure if these should be named vddio_xxx. The > 'pins' properties says these are IO pads, but this does not seem correct. These are IO pads. One IO rail have multiple sub pads to power down some of interface when not used. Like if CSIA is active, we can power down CSIB, CSIC etc. All CSI pads are lined to single IO rail.