Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751780AbcDOPOt (ORCPT ); Fri, 15 Apr 2016 11:14:49 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:6411 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751121AbcDOPOr (ORCPT ); Fri, 15 Apr 2016 11:14:47 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 15 Apr 2016 08:12:55 -0700 Subject: Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control To: Laxman Dewangan , , , , , , References: <1460473007-11535-1-git-send-email-ldewangan@nvidia.com> <1460473007-11535-7-git-send-email-ldewangan@nvidia.com> <5710F7A4.5070902@nvidia.com> <5710F6CA.6060700@nvidia.com> CC: , , , From: Jon Hunter Message-ID: <57110560.80004@nvidia.com> Date: Fri, 15 Apr 2016 16:14:40 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <5710F6CA.6060700@nvidia.com> X-Originating-IP: [10.26.11.193] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4182 Lines: 111 On 15/04/16 15:12, Laxman Dewangan wrote: > > On Friday 15 April 2016 07:46 PM, Jon Hunter wrote: >> On 12/04/16 15:56, Laxman Dewangan wrote: >>> NVIDIA Tegra210 supports the IO pads which can operate at 1.8V >>> or 3.3V I/O voltage levels. Also IO pads can be configured for >>> power down state if it is not in used. SW needs to configure the >>> voltage level of IO pads based on IO rail voltage and its power >>> state based on platform usage. >>> >>> Add DT binding document for detailing the DT properties for >>> configuring IO pads voltage levels and its power state. >>> >>> Signed-off-by: Laxman Dewangan >> [snip] >> >>> +Required subnode-properties: >>> +========================== >>> +- pins : An array of strings. Each string contains the name of an IO >>> pads. Valid >>> + values for these names are listed below. >>> + >>> +Optional subnode-properties: >>> +========================== >>> +-nvidia,io-rail-voltage: Integer. The voltage level of IO pads. The >>> + valid values are 1.8V and 3.3V. Macros are >>> + defined for these voltage levels in >>> + >>> + Use TEGRA210_IO_RAIL_1800000UV for 1.8V >>> + Use TEGRA210_IO_RAIL_3300000UV for 3.3V >>> + >>> +-nvidia,io-pad-deep-power-down: Integer, representing the deep power >>> down state >>> + of the IO pads. If this is enable then IO pads >>> + will be in power down state and interface is not >>> + enabled for any transaction. This is power >>> + saving mode of the IO pads. The macros are >>> + defined for enable/disable in >>> + >>> + TEGRA210_IO_PAD_DEEP_POWER_DOWN_DISABLE for >>> + disable. >>> + TEGRA210_IO_PAD_DEEP_POWER_DOWN_ENABLE for >>> + enable. >>> +Valid values for pin are: >>> + audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, >>> + dbg, debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, >>> + gpio, hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, >>> + pex-ctrl, sdmmc1, sdmmc3, spi, spi-hv, uart, usb-bias, usb0, >>> + usb1, usb2, usb3. >> Thinking about this some more, the above are not IO pads but supply >> pads, AFAICT. And these supply pads, are supplying the voltage to >> various IO pads. I am not sure if these should be named vddio_xxx. The >> 'pins' properties says these are IO pads, but this does not seem correct. > > These are IO pads. One IO rail have multiple sub pads to power down > some of interface when not used. Like if CSIA is active, we can power > down CSIB, CSIC etc. To me, 'IO rail' implies a supply rail, but this is not the same as an IO pad (or pin/ball). And hence, I think the terminology here is confusing. For example, audio_hv powers the following IO pads ... DAP1_DIN DAP1_DOUT DAP1_FS DAP1_SCLK SPI2_MOSI SPI2_MISO SPI2_SCK SPI2_CS0 SPI2_CS1 And sdmmc1 powers the following IO pads ... SDMMC1_CLK SDMMC1_CMD SDMMC1_DAT0 SDMMC1_DAT1 SDMMC1_DAT2 SDMMC1_DAT3 SDMMC1_COMP As for CSIA, I don't think this is a pin/pad at all, but a software means to control the power down for the CSI_A_xxx pads. If CSIA is an IO pad then what is the ball number for Tegra210? In the datasheet I only see ... CSI_A_CLK_N Y6 CSI_A_CLK_P Y7 CSI_A_D0_N Y4 CSI_A_D0_P Y5 CSI_A_D1_N Y1 CSI_A_D1_P AA1 > All CSI pads are lined to single IO rail. I agree with this and from the data-sheet I see the rail that powers the CSI (and DSI) interfaces is called AVDD_DSI_CSI. But again, in the DT document you are referring to csia, csib, csic, csid, csie, csif as pins, but these don't appear to be physical pins, and this appears to be more of a software means to control power to the various csi_x pins. It seems to me that each of the existing CSI_A_xxx pins/pads should be mapped to or register with the appropriate power-down control and when all pads are set to inactive this then triggers the power-down of all the CSI_A_xxx pads. Cheers Jon