Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752155AbcDOPTa (ORCPT ); Fri, 15 Apr 2016 11:19:30 -0400 Received: from mga02.intel.com ([134.134.136.20]:20008 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751121AbcDOPT3 (ORCPT ); Fri, 15 Apr 2016 11:19:29 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,487,1455004800"; d="scan'208";a="945949346" From: kan.liang@intel.com To: peterz@infradead.org, tglx@linutronix.de, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, Kan Liang Subject: [PATCH 1/1] x86, perf: add LBR filter support for SLM Date: Fri, 15 Apr 2016 00:53:45 -0700 Message-Id: <1460706825-46163-1-git-send-email-kan.liang@intel.com> X-Mailer: git-send-email 2.5.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2027 Lines: 69 From: Kan Liang LBR filtering is also supported on the Silvermont and Airmont microarchitectures. The layout of MSR_LBR_SELECT is same as Nehalem. Signed-off-by: Kan Liang --- arch/x86/events/intel/core.c | 2 +- arch/x86/events/intel/lbr.c | 18 ++++++++++++++++++ arch/x86/events/perf_event.h | 2 ++ 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 931c13a..14d27e3 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3581,7 +3581,7 @@ __init int intel_pmu_init(void) memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); - intel_pmu_lbr_init_atom(); + intel_pmu_lbr_init_slm(); x86_pmu.event_constraints = intel_slm_event_constraints; x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index ad26ca7..317e29e 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -1058,6 +1058,24 @@ void __init intel_pmu_lbr_init_atom(void) pr_cont("8-deep LBR, "); } +/* slm */ +void __init intel_pmu_lbr_init_slm(void) +{ + x86_pmu.lbr_nr = 8; + x86_pmu.lbr_tos = MSR_LBR_TOS; + x86_pmu.lbr_from = MSR_LBR_CORE_FROM; + x86_pmu.lbr_to = MSR_LBR_CORE_TO; + + x86_pmu.lbr_sel_mask = LBR_SEL_MASK; + x86_pmu.lbr_sel_map = nhm_lbr_sel_map; + + /* + * SW branch filter usage: + * - compensate for lack of HW filter + */ + pr_cont("8-deep LBR, "); +} + /* Knights Landing */ void intel_pmu_lbr_init_knl(void) { diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 8b78481..7d62a02 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -909,6 +909,8 @@ void intel_pmu_lbr_init_nhm(void); void intel_pmu_lbr_init_atom(void); +void intel_pmu_lbr_init_slm(void); + void intel_pmu_lbr_init_snb(void); void intel_pmu_lbr_init_hsw(void); -- 2.5.0